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Jamin Lin 8107448de7 hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 
The design of INTC controllers has significantly changed in AST2700 A1.

There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged every
32 sources for interrupt numbers greater than 127.

There are two levels of interrupt controllers, INTC(CPUD Die) and INTCIO
(IO Die). The interrupt sources of INTC are the interrupt numbers from INTC_0 to
INTC_127 and interrupts from INTCIO. The interrupt sources of INTCIO are the
interrupt numbers greater than INTC_127. INTC_IO controls the interrupts
INTC_128 to INTC_319 only.

Currently, only GIC 192 to 201 are supported, and their source interrupts are
from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
GIC 192-201.

The design of the orgates for GICINT 196 is as follows:
It has interrupt sources ranging from 0 to 31, with its output pin connected to
INTCIO "T0 GICINT_196". The output pin is then connected to INTC "GIC_192_201"
at bit 4, and its bit 4 output should be connected to GIC 196.
The design of INTC GIC_192_201 have 10 output pins, mapped as following:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196

To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC.
These will be removed if we decide not to support AST2700 A0 in the future.

|-------------------------------------------------------------------------------------------------------|
|                                                   AST2700 A1 Design                                   |
|           To GICINT196                                                                                |
|                                                                                                       |
|   ETH1    |-----------|                    |--------------------------|        |--------------|       |
|  -------->|0          |                    |         INTCIO           |        |  orgates[0]  |       |
|   ETH2    |          4|   orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0            |       |
|  -------->|1         5|   orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1            |       |
|   ETH3    |          6|   orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2            |       |
|  -------->|2        19|   orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3  OR[0:9]   |-----| |
|   UART0   |         20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4            |     | |
|  -------->|7        21|   orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5            |     | |
|   UART1   |         22|   orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6            |     | |
|  -------->|8        23|   orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7            |     | |
|   UART2   |         24|   orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8            |     | |
|  -------->|9        25|   orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9            |     | |
|   UART3   |         26|                    |--------------------------|        |--------------|     | |
|  ---------|10       27|                                                                             | |
|   UART5   |         28|                                                                             | |
|  -------->|11       29|                                                                             | |
|   UART6   |           |                                                                             | |
|  -------->|12       30|     |-----------------------------------------------------------------------| |
|   UART7   |         31|     |                                                                         |
|  -------->|13         |     |                                                                         |
|   UART8   |  OR[0:31] |     |                |------------------------------|           |----------|  |
|  -------->|14         |     |                |            INTC              |           |     GIC  |  |
|   UART9   |           |     |                |inpin[0:0]--------->outpin[0] |---------->|192       |  |
|  -------->|15         |     |                |inpin[0:1]--------->outpin[1] |---------->|193       |  |
|   UART10  |           |     |                |inpin[0:2]--------->outpin[2] |---------->|194       |  |
|  -------->|16         |     |                |inpin[0:3]--------->outpin[3] |---------->|195       |  |
|   UART11  |           |     |--------------> |inpin[0:4]--------->outpin[4] |---------->|196       |  |
|  -------->|17         |                      |inpin[0:5]--------->outpin[5] |---------->|197       |  |
|   UART12  |           |                      |inpin[0:6]--------->outpin[6] |---------->|198       |  |
|  -------->|18         |                      |inpin[0:7]--------->outpin[7] |---------->|199       |  |
|           |-----------|                      |inpin[0:8]--------->outpin[8] |---------->|200       |  |
|                                              |inpin[0:9]--------->outpin[9] |---------->|201       |  |
|-------------------------------------------------------------------------------------------------------|
|-------------------------------------------------------------------------------------------------------|
|  ETH1    |-----------|     orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128       |  |
| -------->|0          |     orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129       |  |
|  ETH2    |          4|     orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130       |  |
| -------->|1         5|     orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131       |  |
|  ETH3    |          6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132       |  |
| -------->|2        19|     orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133       |  |
|  UART0   |         20|     orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134       |  |
| -------->|7        21|     orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135       |  |
|  UART1   |         22|     orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136       |  |
| -------->|8        23|                       |------------------------------|           |----------|  |
|  UART2   |         24|                                                                                |
| -------->|9        25|                       AST2700 A0 Design                                        |
|  UART3   |         26|                                                                                |
| -------->|10       27|                                                                                |
|  UART5   |         28|                                                                                |
| -------->|11       29| GICINT132                                                                      |
|  UART6   |           |                                                                                |
| -------->|12       30|                                                                                |
|  UART7   |         31|                                                                                |
| -------->|13         |                                                                                |
|  UART8   |  OR[0:31] |                                                                                |
| -------->|14         |                                                                                |
|  UART9   |           |                                                                                |
| -------->|15         |                                                                                |
|  UART10  |           |                                                                                |
| -------->|16         |                                                                                |
|  UART11  |           |                                                                                |
| -------->|17         |                                                                                |
|  UART12  |           |                                                                                |
| -------->|18         |                                                                                |
|          |-----------|                                                                                |
|                                                                                                       |
|-------------------------------------------------------------------------------------------------------|

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-22-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09 14:36:53 +01:00
..
allwinner-a10.h include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
allwinner-h3.h include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
allwinner-r40.h include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
armsse-version.h hw/arm/armsse: Introduce SSE subsystem version property 2021-03-08 17:20:01 +00:00
armsse.h hw/arm: Set number of MPU regions correctly for an505, an521, an524 2023-08-31 11:07:02 +01:00
armv7m.h hw/arm/armv7m: alias the NVIC "num-prio-bits" property 2024-01-09 14:42:40 +00:00
aspeed.h hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB 2025-01-27 09:38:15 +01:00
aspeed_soc.h hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 2025-03-09 14:36:53 +01:00
bcm2835_peripherals.h hw/arm: Connect OTP device to BCM2835 2024-07-01 12:48:55 +01:00
bcm2836.h hw/arm/bcm2853_peripherals: Split out common part of peripherals 2024-02-27 13:01:42 +00:00
bcm2838.h hw/arm/bcm2838: Add GIC-400 to BCM2838 SoC 2024-02-27 13:01:42 +00:00
bcm2838_peripherals.h hw/arm/bcm2838_peripherals: Add clock_isp stub 2024-02-27 13:01:42 +00:00
boot.h hw/arm/boot: Propagate vCPU to arm_load_dtb() 2025-02-07 16:09:18 +00:00
bsa.h target/arm: Implement SEL2 physical and virtual timers 2025-03-07 10:08:21 +00:00
digic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
exynos4210.h hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h' 2023-10-19 13:01:52 +01:00
fdt.h hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiation 2015-06-19 14:17:44 +01:00
fsl-imx6.h hw/pci-host/designware: Expose MSI IRQ 2025-01-27 13:50:14 +00:00
fsl-imx6ul.h fsl-imx6ul: Add various missing unimplemented devices 2024-01-26 11:30:49 +00:00
fsl-imx7.h hw/pci-host/designware: Expose MSI IRQ 2025-01-27 13:50:14 +00:00
fsl-imx8mp.h hw/arm/fsl-imx8mp: Add on-chip RAM 2025-02-25 17:24:00 +00:00
fsl-imx25.h hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00
fsl-imx31.h hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header 2023-10-27 12:42:13 +01:00
linux-boot-if.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
msf2-soc.h hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] 2024-02-02 13:51:58 +00:00
npcm7xx.h hw/misc: Move NPCM7XX CLK to NPCM CLK 2025-02-20 15:22:22 +00:00
npcm8xx.h hw/arm: Add NPCM845 Evaluation board 2025-02-20 15:22:22 +00:00
nrf51.h hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition 2020-05-11 11:05:11 +01:00
nrf51_soc.h hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' 2025-01-27 12:58:26 +00:00
omap.h hw/sd/omap_mmc: Use similar API for "wire up omap_clk" to other OMAP devices 2025-01-31 19:36:44 +01:00
primecell.h hw: move headers to include/ 2013-04-08 18:13:10 +02:00
raspberrypi-fw-defs.h hw/misc: Implement mailbox properties for customer OTP and device specific private keys 2024-07-01 12:48:55 +01:00
raspi_platform.h hw/arm: Add memory region for BCM2837 RPiVid ASB 2024-02-27 13:01:42 +00:00
sharpsl.h hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses 2020-07-03 16:59:45 +01:00
smmu-common.h hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper 2025-03-07 10:59:25 +00:00
smmuv3.h hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 2023-05-30 15:50:16 +01:00
soc_dma.h Include exec/memory.h slightly less 2019-08-16 13:31:52 +02:00
stm32f100_soc.h hw/arm/stm32f100: Report error when incorrect CPU is used 2023-11-20 15:30:59 +00:00
stm32f205_soc.h hw/arm/stm32f205: Report error when incorrect CPU is used 2023-11-20 15:30:59 +00:00
stm32f405_soc.h hw/arm/stm32f405: Add RCC device to stm32f405 SoC 2024-10-15 11:29:45 +01:00
stm32l4x5_soc.h hw/arm: Add the USART to the stm32l4x5 SoC 2024-04-25 10:21:59 +01:00
virt.h include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
xen_arch_hvm.h hw/arm: introduce xenpvh machine 2023-06-15 16:46:47 -07:00
xlnx-versal.h hw/arm/xlnx: Connect secondary CGEM IRQs 2024-10-01 13:55:38 +01:00
xlnx-zynqmp.h hw/arm/xlnx: Connect secondary CGEM IRQs 2024-10-01 13:55:38 +01:00