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hw/misc: Move NPCM7XX CLK to NPCM CLK
A lot of NPCM7XX and NPCM8XX CLK modules share the same code, this commit moves the NPCM7XX CLK to NPCM CLK for these properties. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-12-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu
Peter Maydell
parent
c8283b0f4a
commit
ca6d6a94f4
4 changed files with 77 additions and 61 deletions
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@ -198,7 +198,7 @@ static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
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}
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}
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static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
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static void npcm7xx_clk_update_all_plls(NPCMCLKState *clk)
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{
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int i;
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@ -207,7 +207,7 @@ static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
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}
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}
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static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
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static void npcm7xx_clk_update_all_sels(NPCMCLKState *clk)
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{
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int i;
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@ -216,7 +216,7 @@ static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
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}
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}
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static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
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static void npcm7xx_clk_update_all_dividers(NPCMCLKState *clk)
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{
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int i;
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@ -225,7 +225,7 @@ static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
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}
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}
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static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
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static void npcm7xx_clk_update_all_clocks(NPCMCLKState *clk)
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{
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clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
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npcm7xx_clk_update_all_plls(clk);
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@ -635,7 +635,7 @@ static void npcm7xx_clk_divider_init(Object *obj)
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}
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static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
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NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
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NPCMCLKState *clk, const PLLInitInfo *init_info)
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{
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pll->name = init_info->name;
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pll->clk = clk;
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@ -647,7 +647,7 @@ static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
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}
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static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
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NPCM7xxCLKState *clk, const SELInitInfo *init_info)
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NPCMCLKState *clk, const SELInitInfo *init_info)
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{
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int input_size = init_info->input_size;
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@ -664,7 +664,7 @@ static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
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}
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static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
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NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
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NPCMCLKState *clk, const DividerInitInfo *init_info)
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{
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div->name = init_info->name;
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div->clk = clk;
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@ -683,7 +683,7 @@ static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
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}
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}
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static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
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static Clock *npcm7xx_get_clock(NPCMCLKState *clk, ClockSrcType type,
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int index)
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{
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switch (type) {
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@ -700,7 +700,7 @@ static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
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}
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}
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static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
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static void npcm7xx_connect_clocks(NPCMCLKState *clk)
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{
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int i, j;
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Clock *src;
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@ -724,10 +724,10 @@ static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
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}
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}
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static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
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static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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NPCM7xxCLKState *s = opaque;
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NPCMCLKState *s = opaque;
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int64_t now_ns;
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uint32_t value = 0;
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@ -766,19 +766,19 @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
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break;
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};
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trace_npcm7xx_clk_read(offset, value);
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trace_npcm_clk_read(offset, value);
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return value;
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}
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static void npcm7xx_clk_write(void *opaque, hwaddr offset,
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static void npcm_clk_write(void *opaque, hwaddr offset,
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uint64_t v, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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NPCM7xxCLKState *s = opaque;
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NPCMCLKState *s = opaque;
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uint32_t value = v;
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trace_npcm7xx_clk_write(offset, value);
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trace_npcm_clk_write(offset, value);
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if (reg >= NPCM7XX_CLK_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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@ -842,7 +842,7 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
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static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
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int level)
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{
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NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);
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NPCMCLKState *clk = NPCM_CLK(opaque);
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uint32_t rcr;
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g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
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@ -856,9 +856,9 @@ static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
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}
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}
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static const struct MemoryRegionOps npcm7xx_clk_ops = {
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.read = npcm7xx_clk_read,
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.write = npcm7xx_clk_write,
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static const struct MemoryRegionOps npcm_clk_ops = {
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.read = npcm_clk_read,
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.write = npcm_clk_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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@ -867,9 +867,9 @@ static const struct MemoryRegionOps npcm7xx_clk_ops = {
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},
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};
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static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
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static void npcm_clk_enter_reset(Object *obj, ResetType type)
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{
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NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
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NPCMCLKState *s = NPCM_CLK(obj);
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QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
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@ -882,7 +882,7 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
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*/
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}
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static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
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static void npcm7xx_clk_init_clock_hierarchy(NPCMCLKState *s)
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{
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int i;
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@ -918,19 +918,19 @@ static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
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clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
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}
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static void npcm7xx_clk_init(Object *obj)
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static void npcm_clk_init(Object *obj)
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{
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NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
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NPCMCLKState *s = NPCM_CLK(obj);
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memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
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TYPE_NPCM7XX_CLK, 4 * KiB);
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memory_region_init_io(&s->iomem, obj, &npcm_clk_ops, s,
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TYPE_NPCM_CLK, 4 * KiB);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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}
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static int npcm7xx_clk_post_load(void *opaque, int version_id)
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static int npcm_clk_post_load(void *opaque, int version_id)
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{
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if (version_id >= 1) {
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NPCM7xxCLKState *clk = opaque;
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NPCMCLKState *clk = opaque;
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npcm7xx_clk_update_all_clocks(clk);
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}
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@ -938,10 +938,10 @@ static int npcm7xx_clk_post_load(void *opaque, int version_id)
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return 0;
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}
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static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
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static void npcm_clk_realize(DeviceState *dev, Error **errp)
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{
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int i;
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NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
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NPCMCLKState *s = NPCM_CLK(dev);
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qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
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NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
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@ -996,15 +996,15 @@ static const VMStateDescription vmstate_npcm7xx_clk_divider = {
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},
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};
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static const VMStateDescription vmstate_npcm7xx_clk = {
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.name = "npcm7xx-clk",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = npcm7xx_clk_post_load,
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static const VMStateDescription vmstate_npcm_clk = {
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.name = "npcm-clk",
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.version_id = 2,
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.minimum_version_id = 2,
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.post_load = npcm_clk_post_load,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
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VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
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VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
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VMSTATE_UINT32_ARRAY(regs, NPCMCLKState, NPCM_CLK_MAX_NR_REGS),
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VMSTATE_INT64(ref_ns, NPCMCLKState),
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VMSTATE_CLOCK(clkref, NPCMCLKState),
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VMSTATE_END_OF_LIST(),
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},
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};
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@ -1033,17 +1033,23 @@ static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
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dc->vmsd = &vmstate_npcm7xx_clk_divider;
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}
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static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
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static void npcm_clk_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS);
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dc->vmsd = &vmstate_npcm_clk;
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dc->realize = npcm_clk_realize;
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rc->phases.enter = npcm_clk_enter_reset;
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}
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static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
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QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS);
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dc->desc = "NPCM7xx Clock Control Registers";
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dc->vmsd = &vmstate_npcm7xx_clk;
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dc->realize = npcm7xx_clk_realize;
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rc->phases.enter = npcm7xx_clk_enter_reset;
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}
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static const TypeInfo npcm7xx_clk_pll_info = {
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@ -1070,11 +1076,18 @@ static const TypeInfo npcm7xx_clk_divider_info = {
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.class_init = npcm7xx_clk_divider_class_init,
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};
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static const TypeInfo npcm_clk_info = {
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.name = TYPE_NPCM_CLK,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCMCLKState),
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.instance_init = npcm_clk_init,
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.class_init = npcm_clk_class_init,
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.abstract = true,
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};
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static const TypeInfo npcm7xx_clk_info = {
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.name = TYPE_NPCM7XX_CLK,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCM7xxCLKState),
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.instance_init = npcm7xx_clk_init,
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.parent = TYPE_NPCM_CLK,
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.class_init = npcm7xx_clk_class_init,
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};
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@ -1083,6 +1096,7 @@ static void npcm7xx_clk_register_type(void)
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type_register_static(&npcm7xx_clk_pll_info);
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type_register_static(&npcm7xx_clk_sel_info);
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type_register_static(&npcm7xx_clk_divider_info);
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type_register_static(&npcm_clk_info);
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type_register_static(&npcm7xx_clk_info);
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}
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type_init(npcm7xx_clk_register_type);
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@ -130,9 +130,9 @@ mos6522_set_sr_int(void) "set sr_int"
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mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64
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mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x"
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# npcm7xx_clk.c
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npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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# npcm_clk.c
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npcm_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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npcm_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
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# npcm_gcr.c
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npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64
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@ -90,7 +90,7 @@ struct NPCM7xxState {
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MemoryRegion *dram;
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NPCMGCRState gcr;
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NPCM7xxCLKState clk;
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NPCMCLKState clk;
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NPCM7xxTimerCtrlState tim[3];
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NPCM7xxADCState adc;
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NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES];
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@ -20,11 +20,12 @@
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#include "hw/clock.h"
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#include "hw/sysbus.h"
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/*
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* Number of registers in our device state structure. Don't change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
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/*
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* Number of maximum registers in NPCM device state structure. Don't change
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* this without incrementing the version_id in the vmstate.
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*/
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#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS
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#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
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@ -80,7 +81,7 @@ typedef enum NPCM7xxClockDivider {
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NPCM7XX_CLOCK_NR_DIVIDERS,
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} NPCM7xxClockConverter;
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typedef struct NPCM7xxCLKState NPCM7xxCLKState;
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typedef struct NPCMCLKState NPCMCLKState;
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/**
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* struct NPCM7xxClockPLLState - A PLL module in CLK module.
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@ -94,7 +95,7 @@ typedef struct NPCM7xxClockPLLState {
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DeviceState parent;
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const char *name;
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NPCM7xxCLKState *clk;
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NPCMCLKState *clk;
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Clock *clock_in;
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Clock *clock_out;
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@ -115,7 +116,7 @@ typedef struct NPCM7xxClockSELState {
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DeviceState parent;
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const char *name;
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NPCM7xxCLKState *clk;
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NPCMCLKState *clk;
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uint8_t input_size;
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Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
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Clock *clock_out;
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@ -140,7 +141,7 @@ typedef struct NPCM7xxClockDividerState {
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DeviceState parent;
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const char *name;
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NPCM7xxCLKState *clk;
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NPCMCLKState *clk;
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Clock *clock_in;
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Clock *clock_out;
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@ -155,7 +156,7 @@ typedef struct NPCM7xxClockDividerState {
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};
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} NPCM7xxClockDividerState;
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struct NPCM7xxCLKState {
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struct NPCMCLKState {
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SysBusDevice parent;
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MemoryRegion iomem;
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@ -165,7 +166,7 @@ struct NPCM7xxCLKState {
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NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
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NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
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uint32_t regs[NPCM7XX_CLK_NR_REGS];
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uint32_t regs[NPCM_CLK_MAX_NR_REGS];
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/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
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int64_t ref_ns;
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@ -174,7 +175,8 @@ struct NPCM7xxCLKState {
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Clock *clkref;
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};
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#define TYPE_NPCM_CLK "npcm-clk"
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OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK)
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#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
|
||||
|
||||
#endif /* NPCM_CLK_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue