Commit graph

4 commits

Author SHA1 Message Date
Thomas Huth
fcf5ef2ab5 Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-12-20 21:52:12 +01:00
Rabin Vincent
ceffd34e85 target-cris: add v17 CPU
In the CRIS v17 CPU an ADDC (add with carry) instruction has been added
compared to the v10 instruction set.

 Assembler syntax:

  ADDC [Rs],Rd
  ADDC [Rs+],Rd

 Size: Dword

 Description:

  The source data is added together with the carry flag to the
  destination register. The size of the operation is dword.

 Operation:

  Rd += s + C-flag;

 Flags affected:

  S R P U I X N Z V C
  - - - - - 0 * * * *

 Instruction format: ADDC [Rs],Rd

  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |Destination(Rd)| 1   0   0   1   1   0   1   0 |   Source(Rs)  |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

 Instruction format: ADDC [Rs+],Rd

  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |Destination(Rd)| 1   1   0   1   1   0   1   0 |   Source(Rs)  |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

[EI: Shorten 80+ lines]
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-09-28 11:30:59 +02:00
Blue Swirl
70539e1850 Update to a hopefully more future proof FSF address
See also 8167ee8839,
530e7615ce and
fad6cb1a56.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-07 15:48:43 +00:00
Edgar E. Iglesias
40e9eddd38 cris: Add support for CRISv10 translation.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-02-15 12:18:57 +01:00