2 commits

Author	SHA1	Message	Date
Alistair Francis	57a3a62265	hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines ... Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com	2021-09-21 07:56:49 +10:00
Alistair Francis	df41cbd6bf	hw/timer: Initial commit of Ibex Timer ... Add support for the Ibex timer. This is used with the RISC-V mtime/mtimecmp similar to the SiFive CLINT. We currently don't support changing the prescale or the timervalue. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com	2021-06-24 05:00:12 -07:00