3 commits

Author	SHA1	Message	Date
Alistair Francis	f436ecc315	hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines ... Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com	2021-09-21 07:56:49 +10:00
Yifei Jiang	dbd3ec548a	target/riscv: Add sifive_plic vmstate ... Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-7-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	2020-11-03 07:17:23 -08:00
Bin Meng	801da1701c	hw/intc: Move sifive_plic.h to the include directory ... Since sifive_plic.h is used by hw/intc/sifive_plic.c, it has to be in the public include directory. Move it. Fixes: 84fcf3c151 ("hw/riscv: Move sifive_plic model to hw/intc") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1602578033-68384-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	2020-10-22 12:00:22 -07:00

Renamed from hw/intc/sifive_plic.h (Browse further)