3 commits

Author	SHA1	Message	Date
Richard Henderson	99f4ec6eab	tcg/riscv: Support ANDN, ORN, XNOR from Zbb ... Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2023-05-25 13:57:52 +00:00
Richard Henderson	f0f43534f7	tcg/riscv: Simplify constraints on qemu_ld/st ... The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2023-05-11 09:53:41 +01:00
Richard Henderson	fc63a4c5c8	tcg/riscv: Split out target constraints to tcg-target-con-str.h ... Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2021-02-02 12:12:31 -10:00