3 commits

Author	SHA1	Message	Date
Joel Sing	c13b169f1a	RISC-V: Clear load reservations on context switch and SC ... This prevents a load reservation from being placed in one context/process, then being used in another, resulting in an SC succeeding incorrectly and breaking atomics. Signed-off-by: Joel Sing <joel@sing.id.au> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	2019-06-25 22:37:04 -07:00
Bastian Koppelmann	40b9faecfe	target/riscv: Convert RV64A insns to decodetree ... Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>	2019-03-13 10:34:06 +01:00
Bastian Koppelmann	3b77c289ae	target/riscv: Convert RV32A insns to decodetree ... Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>	2019-03-13 10:34:06 +01:00