1 commit

Author	SHA1	Message	Date
Bin Meng	9fe640a53d	hw/riscv: Move sifive_u_prci model to hw/misc ... This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_u_prci model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	2020-09-09 15:54:19 -07:00

Renamed from include/hw/riscv/sifive_u_prci.h (Browse further)