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hw/usb/uhci: Introduce and use register defines

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Introduce defines for UHCI registers to simplify adding register access
in subsequent patches of the series.

No functional change.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-ID: <20240906122542.3808997-3-linux@roeck-us.net>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Guenter Roeck 2024-09-06 05:25:36 -07:00 • committed by Philippe Mathieu-Daudé
parent 9d59b65d82
commit d826e47404
2 changed files with 27 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

32
hw/usb/hcd-uhci.c
View file

@ -389,7 +389,7 @@ static void uhci_port_write(void *opaque, hwaddr addr,
trace_usb_uhci_mmio_writew(addr, val); trace_usb_uhci_mmio_writew(addr, val);
switch (addr) { switch (addr) {
case 0x00: case UHCI_USBCMD:
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
/* start frame processing */ /* start frame processing */
trace_usb_uhci_schedule_start(); trace_usb_uhci_schedule_start();
@ -424,7 +424,7 @@ static void uhci_port_write(void *opaque, hwaddr addr,
} }
} }
break; break;
case 0x02: case UHCI_USBSTS:
s->status &= ~val; s->status &= ~val;
/* /*
* XXX: the chip spec is not coherent, so we add a hidden * XXX: the chip spec is not coherent, so we add a hidden
@ -435,27 +435,27 @@ static void uhci_port_write(void *opaque, hwaddr addr,
} }
uhci_update_irq(s); uhci_update_irq(s);
break; break;
case 0x04: case UHCI_USBINTR:
s->intr = val; s->intr = val;
uhci_update_irq(s); uhci_update_irq(s);
break; break;
case 0x06: case UHCI_USBFRNUM:
if (s->status & UHCI_STS_HCHALTED) { if (s->status & UHCI_STS_HCHALTED) {
s->frnum = val & 0x7ff; s->frnum = val & 0x7ff;
} }
break; break;
case 0x08: case UHCI_USBFLBASEADD:
s->fl_base_addr &= 0xffff0000; s->fl_base_addr &= 0xffff0000;
s->fl_base_addr |= val & ~0xfff; s->fl_base_addr |= val & ~0xfff;
break; break;
case 0x0a: case UHCI_USBFLBASEADD + 2:
s->fl_base_addr &= 0x0000ffff; s->fl_base_addr &= 0x0000ffff;
s->fl_base_addr |= (val << 16); s->fl_base_addr |= (val << 16);
break; break;
case 0x0c: case UHCI_USBSOF:
s->sof_timing = val & 0xff; s->sof_timing = val & 0xff;
break; break;
case 0x10 ... 0x1f: case UHCI_USBPORTSC1 ... UHCI_USBPORTSC4:
{ {
UHCIPort *port; UHCIPort *port;
USBDevice *dev; USBDevice *dev;
@ -493,28 +493,28 @@ static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
uint32_t val; uint32_t val;
switch (addr) { switch (addr) {
case 0x00: case UHCI_USBCMD:
val = s->cmd; val = s->cmd;
break; break;
case 0x02: case UHCI_USBSTS:
val = s->status; val = s->status;
break; break;
case 0x04: case UHCI_USBINTR:
val = s->intr; val = s->intr;
break; break;
case 0x06: case UHCI_USBFRNUM:
val = s->frnum; val = s->frnum;
break; break;
case 0x08: case UHCI_USBFLBASEADD:
val = s->fl_base_addr & 0xffff; val = s->fl_base_addr & 0xffff;
break; break;
case 0x0a: case UHCI_USBFLBASEADD + 2:
val = (s->fl_base_addr >> 16) & 0xffff; val = (s->fl_base_addr >> 16) & 0xffff;
break; break;
case 0x0c: case UHCI_USBSOF:
val = s->sof_timing; val = s->sof_timing;
break; break;
case 0x10 ... 0x1f: case UHCI_USBPORTSC1 ... UHCI_USBPORTSC4:
{ {
UHCIPort *port; UHCIPort *port;
int n; int n;

11
include/hw/usb/uhci-regs.h
View file

@ -1,6 +1,17 @@
#ifndef HW_USB_UHCI_REGS_H #ifndef HW_USB_UHCI_REGS_H
#define HW_USB_UHCI_REGS_H #define HW_USB_UHCI_REGS_H
#define UHCI_USBCMD 0
#define UHCI_USBSTS 2
#define UHCI_USBINTR 4
#define UHCI_USBFRNUM 6
#define UHCI_USBFLBASEADD 8
#define UHCI_USBSOF 0x0c
#define UHCI_USBPORTSC1 0x10
#define UHCI_USBPORTSC2 0x12
#define UHCI_USBPORTSC3 0x14
#define UHCI_USBPORTSC4 0x16
#define UHCI_CMD_FGR (1 << 4) #define UHCI_CMD_FGR (1 << 4)
#define UHCI_CMD_EGSM (1 << 3) #define UHCI_CMD_EGSM (1 << 3)
#define UHCI_CMD_GRESET (1 << 2) #define UHCI_CMD_GRESET (1 << 2)