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hw/usb/uhci: checkpatch cleanup
Fix reported checkpatch issues to prepare for next patches in the series. No functional change. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20240906122542.3808997-2-linux@roeck-us.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Guenter Roeck
Philippe Mathieu-Daudé
parent
4daf88c165
commit
9d59b65d82
1 changed files with 56 additions and 34 deletions
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@ -67,7 +67,7 @@ struct UHCIPCIDeviceClass {
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UHCIInfo info;
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};
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/*
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/*
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* Pending async transaction.
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* 'packet' must be the first field because completion
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* handler does "(UHCIAsync *) pkt" cast.
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@ -220,8 +220,9 @@ static void uhci_async_cancel(UHCIAsync *async)
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uhci_async_unlink(async);
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trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
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async->done);
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if (!async->done)
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if (!async->done) {
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usb_cancel_packet(&async->packet);
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}
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uhci_async_free(async);
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}
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@ -322,7 +323,7 @@ static void uhci_reset(DeviceState *dev)
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s->fl_base_addr = 0;
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s->sof_timing = 64;
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for(i = 0; i < UHCI_PORTS; i++) {
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for (i = 0; i < UHCI_PORTS; i++) {
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port = &s->ports[i];
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port->ctrl = 0x0080;
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if (port->port.dev && port->port.dev->attached) {
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@ -387,7 +388,7 @@ static void uhci_port_write(void *opaque, hwaddr addr,
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trace_usb_uhci_mmio_writew(addr, val);
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switch(addr) {
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switch (addr) {
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case 0x00:
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if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
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/* start frame processing */
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@ -404,7 +405,7 @@ static void uhci_port_write(void *opaque, hwaddr addr,
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int i;
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/* send reset on the USB bus */
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for(i = 0; i < UHCI_PORTS; i++) {
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for (i = 0; i < UHCI_PORTS; i++) {
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port = &s->ports[i];
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usb_device_reset(port->port.dev);
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}
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@ -425,10 +426,13 @@ static void uhci_port_write(void *opaque, hwaddr addr,
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break;
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case 0x02:
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s->status &= ~val;
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/* XXX: the chip spec is not coherent, so we add a hidden
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register to distinguish between IOC and SPD */
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if (val & UHCI_STS_USBINT)
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/*
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* XXX: the chip spec is not coherent, so we add a hidden
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* register to distinguish between IOC and SPD
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*/
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if (val & UHCI_STS_USBINT) {
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s->status2 = 0;
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}
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uhci_update_irq(s);
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break;
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case 0x04:
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@ -436,8 +440,9 @@ static void uhci_port_write(void *opaque, hwaddr addr,
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uhci_update_irq(s);
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break;
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case 0x06:
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if (s->status & UHCI_STS_HCHALTED)
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if (s->status & UHCI_STS_HCHALTED) {
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s->frnum = val & 0x7ff;
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}
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break;
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case 0x08:
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s->fl_base_addr &= 0xffff0000;
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@ -464,8 +469,8 @@ static void uhci_port_write(void *opaque, hwaddr addr,
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dev = port->port.dev;
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if (dev && dev->attached) {
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/* port reset */
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if ( (val & UHCI_PORT_RESET) &&
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!(port->ctrl & UHCI_PORT_RESET) ) {
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if ((val & UHCI_PORT_RESET) &&
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!(port->ctrl & UHCI_PORT_RESET)) {
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usb_device_reset(dev);
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}
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}
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@ -487,7 +492,7 @@ static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
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UHCIState *s = opaque;
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uint32_t val;
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switch(addr) {
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switch (addr) {
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case 0x00:
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val = s->cmd;
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break;
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@ -533,12 +538,13 @@ static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
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}
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/* signal resume if controller suspended */
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static void uhci_resume (void *opaque)
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static void uhci_resume(void *opaque)
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{
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UHCIState *s = (UHCIState *)opaque;
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if (!s)
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if (!s) {
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return;
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}
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if (s->cmd & UHCI_CMD_EGSM) {
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s->cmd |= UHCI_CMD_FGR;
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@ -674,7 +680,8 @@ static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
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return ret;
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}
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static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
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static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async,
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uint32_t *int_mask)
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{
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int len = 0, max_len;
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uint8_t pid;
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@ -682,8 +689,9 @@ static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_
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max_len = ((td->token >> 21) + 1) & 0x7ff;
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pid = td->token & 0xff;
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if (td->ctrl & TD_CTRL_IOS)
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if (td->ctrl & TD_CTRL_IOS) {
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td->ctrl &= ~TD_CTRL_ACTIVE;
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}
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if (async->packet.status != USB_RET_SUCCESS) {
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return uhci_handle_td_error(s, td, async->td_addr,
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@ -693,12 +701,15 @@ static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_
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len = async->packet.actual_length;
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td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
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/* The NAK bit may have been set by a previous frame, so clear it
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here. The docs are somewhat unclear, but win2k relies on this
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behavior. */
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/*
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* The NAK bit may have been set by a previous frame, so clear it
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* here. The docs are somewhat unclear, but win2k relies on this
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* behavior.
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*/
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td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
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if (td->ctrl & TD_CTRL_IOC)
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if (td->ctrl & TD_CTRL_IOC) {
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*int_mask |= 0x01;
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}
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if (pid == USB_TOKEN_IN) {
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pci_dma_write(&s->dev, td->buffer, async->buf, len);
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@ -780,9 +791,11 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
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if (async) {
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if (queuing) {
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/* we are busy filling the queue, we are not prepared
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to consume completed packages then, just leave them
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in async state */
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/*
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* we are busy filling the queue, we are not prepared
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* to consume completed packages then, just leave them
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* in async state
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*/
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return TD_RESULT_ASYNC_CONT;
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}
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if (!async->done) {
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@ -832,7 +845,7 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
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}
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usb_packet_addbuf(&async->packet, async->buf, max_len);
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switch(pid) {
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switch (pid) {
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case USB_TOKEN_OUT:
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case USB_TOKEN_SETUP:
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pci_dma_read(&s->dev, td->buffer, async->buf, max_len);
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@ -911,12 +924,15 @@ static void qhdb_reset(QhDb *db)
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static int qhdb_insert(QhDb *db, uint32_t addr)
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{
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int i;
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for (i = 0; i < db->count; i++)
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if (db->addr[i] == addr)
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for (i = 0; i < db->count; i++) {
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if (db->addr[i] == addr) {
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return 1;
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}
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}
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if (db->count >= UHCI_MAX_QUEUES)
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if (db->count >= UHCI_MAX_QUEUES) {
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return 1;
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}
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db->addr[db->count++] = addr;
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return 0;
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@ -970,8 +986,10 @@ static void uhci_process_frame(UHCIState *s)
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for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
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if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) {
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/* We've reached the usb 1.1 bandwidth, which is
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1280 bytes/frame, stop processing */
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/*
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* We've reached the usb 1.1 bandwidth, which is
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* 1280 bytes/frame, stop processing
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*/
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trace_usb_uhci_frame_stop_bandwidth();
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break;
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}
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@ -1120,8 +1138,10 @@ static void uhci_frame_timer(void *opaque)
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uhci_async_validate_begin(s);
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uhci_process_frame(s);
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uhci_async_validate_end(s);
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/* The spec says frnum is the frame currently being processed, and
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* the guest must look at frnum - 1 on interrupt, so inc frnum now */
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/*
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* The spec says frnum is the frame currently being processed, and
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* the guest must look at frnum - 1 on interrupt, so inc frnum now
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*/
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s->frnum = (s->frnum + 1) & 0x7ff;
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s->expire_time += frame_t;
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}
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@ -1174,7 +1194,7 @@ void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
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if (s->masterbus) {
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USBPort *ports[UHCI_PORTS];
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for(i = 0; i < UHCI_PORTS; i++) {
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for (i = 0; i < UHCI_PORTS; i++) {
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ports[i] = &s->ports[i].port;
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}
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usb_register_companion(s->masterbus, ports, UHCI_PORTS,
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@ -1200,8 +1220,10 @@ void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
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memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,
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"uhci", 0x20);
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/* Use region 4 for consistency with real hardware. BSD guests seem
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to rely on this. */
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/*
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* Use region 4 for consistency with real hardware. BSD guests seem
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* to rely on this.
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*/
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pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
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}
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