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hw/misc: Add nr_regs and cold_reset_values to NPCM CLK

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These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-13-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu 2025-02-19 10:46:03 -08:00 • committed by Peter Maydell
parent ca6d6a94f4
commit cf76c4e174
3 changed files with 22 additions and 7 deletions
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18
hw/misc/npcm_clk.c
View file

@ -81,7 +81,7 @@ enum NPCM7xxCLKRegisters {
* All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
* core domain reset, but this reset type is not yet supported by QEMU.
*/
static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
[NPCM7XX_CLK_CLKEN1] = 0xffffffff,
[NPCM7XX_CLK_CLKSEL] = 0x004aaaaa,
[NPCM7XX_CLK_CLKDIV1] = 0x5413f855,
@ -728,10 +728,11 @@ static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
NPCMCLKState *s = opaque;
NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
int64_t now_ns;
uint32_t value = 0;
if (reg >= NPCM7XX_CLK_NR_REGS) {
if (reg >= c->nr_regs) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
__func__, offset);
@ -776,11 +777,12 @@ static void npcm_clk_write(void *opaque, hwaddr offset,
{
uint32_t reg = offset / sizeof(uint32_t);
NPCMCLKState *s = opaque;
NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
uint32_t value = v;
trace_npcm_clk_write(offset, value);
if (reg >= NPCM7XX_CLK_NR_REGS) {
if (reg >= c->nr_regs) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
__func__, offset);
@ -870,10 +872,10 @@ static const struct MemoryRegionOps npcm_clk_ops = {
static void npcm_clk_enter_reset(Object *obj, ResetType type)
{
NPCMCLKState *s = NPCM_CLK(obj);
NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
g_assert(sizeof(s->regs) >= c->nr_regs * sizeof(uint32_t));
memcpy(s->regs, c->cold_reset_values, sizeof(s->regs));
s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
npcm7xx_clk_update_all_clocks(s);
/*
@ -1045,11 +1047,14 @@ static void npcm_clk_class_init(ObjectClass *klass, void *data)
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
{
NPCMCLKClass *c = NPCM_CLK_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS);
dc->desc = "NPCM7xx Clock Control Registers";
c->nr_regs = NPCM7XX_CLK_NR_REGS;
c->cold_reset_values = npcm7xx_cold_reset_values;
}
static const TypeInfo npcm7xx_clk_pll_info = {
@ -1081,6 +1086,7 @@ static const TypeInfo npcm_clk_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCMCLKState),
.instance_init = npcm_clk_init,
.class_size = sizeof(NPCMCLKClass),
.class_init = npcm_clk_class_init,
.abstract = true,
};

2
hw/misc/npcm_gcr.c
View file

@ -215,6 +215,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
break;
case 8:
g_assert(!(reg & 1));
value = deposit64(s->regs[reg], 32, 32, s->regs[reg + 1]);
break;
@ -270,6 +271,7 @@ static void npcm_gcr_write(void *opaque, hwaddr offset,
break;
case 8:
g_assert(!(reg & 1));
s->regs[reg] = value;
s->regs[reg + 1] = extract64(v, 32, 32);
break;

9
include/hw/misc/npcm_clk.h
View file

@ -175,8 +175,15 @@ struct NPCMCLKState {
Clock *clkref;
};
typedef struct NPCMCLKClass {
SysBusDeviceClass parent;
size_t nr_regs;
const uint32_t *cold_reset_values;
} NPCMCLKClass;
#define TYPE_NPCM_CLK "npcm-clk"
OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK)
OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK)
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
#endif /* NPCM_CLK_H */