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tcg: Merge INDEX_op_mulsh_{i32,i64}

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-07 11:19:29 -08:00
parent a9983f8129
commit c742824dd8
5 changed files with 15 additions and 22 deletions
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2
docs/devel/tcg-ops.rst
View file

@ -589,7 +589,7 @@ Multiword arithmetic support
- | Similar to mulu2, except the two inputs *t1* and *t2* are signed.
* - mulsh_i32/i64 *t0*, *t1*, *t2*
* - mulsh *t0*, *t1*, *t2*
muluh *t0*, *t1*, *t2*

3
include/tcg/tcg-opc.h
View file

@ -44,6 +44,7 @@ DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(eqv, 1, 2, 0, TCG_OPF_INT)
DEF(mul, 1, 2, 0, TCG_OPF_INT)
DEF(mulsh, 1, 2, 0, TCG_OPF_INT)
DEF(muluh, 1, 2, 0, TCG_OPF_INT)
DEF(nand, 1, 2, 0, TCG_OPF_INT)
DEF(neg, 1, 1, 0, TCG_OPF_INT)
@ -90,7 +91,6 @@ DEF(add2_i32, 2, 4, 0, 0)
DEF(sub2_i32, 2, 4, 0, 0)
DEF(mulu2_i32, 2, 2, 0, 0)
DEF(muls2_i32, 2, 2, 0, 0)
DEF(mulsh_i32, 1, 2, 0, 0)
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
DEF(setcond2_i32, 1, 4, 1, 0)
@ -151,7 +151,6 @@ DEF(add2_i64, 2, 4, 0, 0)
DEF(sub2_i64, 2, 4, 0, 0)
DEF(mulu2_i64, 2, 2, 0, 0)
DEF(muls2_i64, 2, 2, 0, 0)
DEF(mulsh_i64, 1, 2, 0, 0)
#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)

10
tcg/optimize.c
View file

@ -549,10 +549,10 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
mulu64(&l64, &h64, x, y);
return h64;
case INDEX_op_mulsh_i32:
return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
case INDEX_op_mulsh_i64:
case INDEX_op_mulsh:
if (type == TCG_TYPE_I32) {
return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
}
muls64(&l64, &h64, x, y);
return h64;
@ -2969,7 +2969,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_mul:
done = fold_mul(&ctx, op);
break;
CASE_OP_32_64(mulsh):
case INDEX_op_mulsh:
case INDEX_op_muluh:
done = fold_mul_highpart(&ctx, op);
break;

8
tcg/tcg-op.c
View file

@ -1156,10 +1156,10 @@ void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_muls2_i32) {
tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_mulsh_i32, TCG_TYPE_I32, 0)) {
} else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I32, 0)) {
TCGv_i32 t = tcg_temp_ebb_new_i32();
tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2);
tcg_gen_op3_i32(INDEX_op_mulsh_i32, rh, arg1, arg2);
tcg_gen_op3_i32(INDEX_op_mulsh, rh, arg1, arg2);
tcg_gen_mov_i32(rl, t);
tcg_temp_free_i32(t);
} else if (TCG_TARGET_REG_BITS == 32) {
@ -2861,10 +2861,10 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_HAS_muls2_i64) {
tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_mulsh_i64, TCG_TYPE_I64, 0)) {
} else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I64, 0)) {
TCGv_i64 t = tcg_temp_ebb_new_i64();
tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2);
tcg_gen_op3_i64(INDEX_op_mulsh_i64, rh, arg1, arg2);
tcg_gen_op3_i64(INDEX_op_mulsh, rh, arg1, arg2);
tcg_gen_mov_i64(rl, t);
tcg_temp_free_i64(t);
} else if (TCG_TARGET_HAS_mulu2_i64 ||

14
tcg/tcg.c
View file

@ -1022,8 +1022,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
OUTOP(INDEX_op_mulsh_i32, TCGOutOpBinary, outop_mulsh),
OUTOP(INDEX_op_mulsh_i64, TCGOutOpBinary, outop_mulsh),
OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh),
OUTOP(INDEX_op_muluh, TCGOutOpBinary, outop_muluh),
OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
@ -4028,18 +4027,14 @@ liveness_pass_1(TCGContext *s)
goto do_not_remove;
case INDEX_op_muls2_i32:
case INDEX_op_muls2_i64:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_mulsh_i32;
opc_new2 = INDEX_op_mulsh;
goto do_mul2;
case INDEX_op_mulu2_i32:
case INDEX_op_mulu2_i64:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_muluh;
goto do_mul2;
case INDEX_op_muls2_i64:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_mulsh_i64;
goto do_mul2;
do_mul2:
nb_iargs = 2;
nb_oargs = 2;
@ -5424,8 +5419,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_andc:
case INDEX_op_eqv:
case INDEX_op_mul:
case INDEX_op_mulsh_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_mulsh:
case INDEX_op_muluh:
case INDEX_op_nand:
case INDEX_op_nor: