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hw/net/xilinx_ethlite: Access TX_LEN register for each port

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Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_LEN. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.

Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now
unused. Not a concern, this array will soon disappear.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-14-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-11-09 19:48:36 +01:00
parent 64fdbae7e1
commit c629791859
1 changed files with 6 additions and 2 deletions
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8
hw/net/xilinx_ethlite.c
View file

@ -62,6 +62,7 @@
typedef struct XlnxXpsEthLitePort {
struct {
uint32_t tx_len;
uint32_t tx_gie;
uint32_t rx_ctrl;
@ -133,6 +134,9 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
case R_TX_LEN0:
case R_TX_LEN1:
r = s->port[port_index].reg.tx_len;
break;
case R_TX_CTRL1:
case R_TX_CTRL0:
r = s->regs[addr];
@ -170,7 +174,7 @@ eth_write(void *opaque, hwaddr addr,
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
txbuf_ptr(s, port_index),
s->regs[base + R_TX_LEN0]);
s->port[port_index].reg.tx_len);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
@ -195,7 +199,7 @@ eth_write(void *opaque, hwaddr addr,
case R_TX_LEN0:
case R_TX_LEN1:
s->regs[addr] = value;
s->port[port_index].reg.tx_len = value;
break;
case R_TX_GIE0: