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hw/net/xilinx_ethlite: Access TX_GIE register for each port

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Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_GIE. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.

Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now
unused. Not a concern, this array will soon disappear.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-13-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-11-09 19:45:58 +01:00
parent 785fd1a9af
commit 64fdbae7e1
1 changed files with 10 additions and 2 deletions
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12
hw/net/xilinx_ethlite.c
View file

@ -62,6 +62,8 @@
typedef struct XlnxXpsEthLitePort {
struct {
uint32_t tx_gie;
uint32_t rx_ctrl;
} reg;
} XlnxXpsEthLitePort;
@ -90,7 +92,7 @@ struct XlnxXpsEthLite
static inline void eth_pulse_irq(XlnxXpsEthLite *s)
{
/* Only the first gie reg is active. */
if (s->regs[R_TX_GIE0] & GIE_GIE) {
if (s->port[0].reg.tx_gie & GIE_GIE) {
qemu_irq_pulse(s->irq);
}
}
@ -126,6 +128,9 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
switch (addr)
{
case R_TX_GIE0:
r = s->port[port_index].reg.tx_gie;
break;
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_CTRL1:
@ -190,10 +195,13 @@ eth_write(void *opaque, hwaddr addr,
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
s->regs[addr] = value;
break;
case R_TX_GIE0:
s->port[port_index].reg.tx_gie = value;
break;
default:
s->regs[addr] = tswap32(value);
break;