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hw/intc/aspeed: Add support for AST2700 TSP INTC
- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the TSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:
- AST2700
Support GICINT128 to GICINT136 in INTC
The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-tsp
Support TSPINT128 to TSPINT136 in INTC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I3f3aca4b90129640369cf4a92deb4b9a12df5b70
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-5-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Steven Lee
Cédric Le Goater
parent
8872b6717c
commit
c528f10dce
2 changed files with 209 additions and 2 deletions
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@ -106,6 +106,51 @@ REG32(SSPINT164_STATUS, 0x1C4)
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REG32(SSPINT165_EN, 0x1D0)
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REG32(SSPINT165_STATUS, 0x1D4)
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/*
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* TSP INTC Registers
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*/
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REG32(TSPINT128_EN, 0x3000)
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REG32(TSPINT128_STATUS, 0x3004)
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REG32(TSPINT129_EN, 0x3100)
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REG32(TSPINT129_STATUS, 0x3104)
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REG32(TSPINT130_EN, 0x3200)
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REG32(TSPINT130_STATUS, 0x3204)
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REG32(TSPINT131_EN, 0x3300)
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REG32(TSPINT131_STATUS, 0x3304)
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REG32(TSPINT132_EN, 0x3400)
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REG32(TSPINT132_STATUS, 0x3404)
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REG32(TSPINT133_EN, 0x3500)
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REG32(TSPINT133_STATUS, 0x3504)
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REG32(TSPINT134_EN, 0x3600)
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REG32(TSPINT134_STATUS, 0x3604)
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REG32(TSPINT135_EN, 0x3700)
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REG32(TSPINT135_STATUS, 0x3704)
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REG32(TSPINT136_EN, 0x3800)
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REG32(TSPINT136_STATUS, 0x3804)
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REG32(TSPINT137_EN, 0x3900)
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REG32(TSPINT137_STATUS, 0x3904)
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REG32(TSPINT138_EN, 0x3A00)
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REG32(TSPINT138_STATUS, 0x3A04)
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REG32(TSPINT160_169_EN, 0x3B00)
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REG32(TSPINT160_169_STATUS, 0x3B04)
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/*
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* TSP INTCIO Registers
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*/
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REG32(TSPINT160_EN, 0x200)
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REG32(TSPINT160_STATUS, 0x204)
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REG32(TSPINT161_EN, 0x210)
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REG32(TSPINT161_STATUS, 0x214)
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REG32(TSPINT162_EN, 0x220)
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REG32(TSPINT162_STATUS, 0x224)
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REG32(TSPINT163_EN, 0x230)
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REG32(TSPINT163_STATUS, 0x234)
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REG32(TSPINT164_EN, 0x240)
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REG32(TSPINT164_STATUS, 0x244)
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REG32(TSPINT165_EN, 0x250)
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REG32(TSPINT165_STATUS, 0x254)
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static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
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uint32_t reg)
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{
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@ -534,8 +579,48 @@ static void aspeed_ssp_intc_write(void *opaque, hwaddr offset, uint64_t data,
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s->regs[reg] = data;
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break;
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}
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}
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return;
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static void aspeed_tsp_intc_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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AspeedINTCState *s = ASPEED_INTC(opaque);
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const char *name = object_get_typename(OBJECT(s));
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uint32_t reg = offset >> 2;
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trace_aspeed_intc_write(name, offset, size, data);
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switch (reg) {
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case R_TSPINT128_EN:
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case R_TSPINT129_EN:
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case R_TSPINT130_EN:
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case R_TSPINT131_EN:
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case R_TSPINT132_EN:
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case R_TSPINT133_EN:
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case R_TSPINT134_EN:
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case R_TSPINT135_EN:
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case R_TSPINT136_EN:
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case R_TSPINT160_169_EN:
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aspeed_intc_enable_handler(s, offset, data);
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break;
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case R_TSPINT128_STATUS:
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case R_TSPINT129_STATUS:
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case R_TSPINT130_STATUS:
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case R_TSPINT131_STATUS:
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case R_TSPINT132_STATUS:
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case R_TSPINT133_STATUS:
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case R_TSPINT134_STATUS:
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case R_TSPINT135_STATUS:
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case R_TSPINT136_STATUS:
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aspeed_intc_status_handler(s, offset, data);
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break;
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case R_TSPINT160_169_STATUS:
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aspeed_intc_status_handler_multi_outpins(s, offset, data);
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break;
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default:
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s->regs[reg] = data;
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break;
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}
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}
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static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
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@ -614,8 +699,38 @@ static void aspeed_ssp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
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s->regs[reg] = data;
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break;
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}
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}
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return;
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static void aspeed_tsp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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AspeedINTCState *s = ASPEED_INTC(opaque);
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const char *name = object_get_typename(OBJECT(s));
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uint32_t reg = offset >> 2;
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trace_aspeed_intc_write(name, offset, size, data);
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switch (reg) {
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case R_TSPINT160_EN:
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case R_TSPINT161_EN:
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case R_TSPINT162_EN:
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case R_TSPINT163_EN:
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case R_TSPINT164_EN:
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case R_TSPINT165_EN:
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aspeed_intc_enable_handler(s, offset, data);
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break;
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case R_TSPINT160_STATUS:
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case R_TSPINT161_STATUS:
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case R_TSPINT162_STATUS:
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case R_TSPINT163_STATUS:
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case R_TSPINT164_STATUS:
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case R_TSPINT165_STATUS:
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aspeed_intc_status_handler(s, offset, data);
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break;
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default:
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s->regs[reg] = data;
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break;
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}
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}
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static const MemoryRegionOps aspeed_intc_ops = {
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@ -658,6 +773,26 @@ static const MemoryRegionOps aspeed_ssp_intcio_ops = {
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}
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};
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static const MemoryRegionOps aspeed_tsp_intc_ops = {
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.read = aspeed_intc_read,
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.write = aspeed_tsp_intc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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}
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};
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static const MemoryRegionOps aspeed_tsp_intcio_ops = {
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.read = aspeed_intcio_read,
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.write = aspeed_tsp_intcio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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}
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};
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static void aspeed_intc_instance_init(Object *obj)
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{
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AspeedINTCState *s = ASPEED_INTC(obj);
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@ -883,6 +1018,74 @@ static const TypeInfo aspeed_2700ssp_intcio_info = {
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.class_init = aspeed_2700ssp_intcio_class_init,
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};
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static AspeedINTCIRQ aspeed_2700tsp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
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{0, 0, 10, R_TSPINT160_169_EN, R_TSPINT160_169_STATUS},
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{1, 10, 1, R_TSPINT128_EN, R_TSPINT128_STATUS},
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{2, 11, 1, R_TSPINT129_EN, R_TSPINT129_STATUS},
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{3, 12, 1, R_TSPINT130_EN, R_TSPINT130_STATUS},
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{4, 13, 1, R_TSPINT131_EN, R_TSPINT131_STATUS},
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{5, 14, 1, R_TSPINT132_EN, R_TSPINT132_STATUS},
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{6, 15, 1, R_TSPINT133_EN, R_TSPINT133_STATUS},
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{7, 16, 1, R_TSPINT134_EN, R_TSPINT134_STATUS},
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{8, 17, 1, R_TSPINT135_EN, R_TSPINT135_STATUS},
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{9, 18, 1, R_TSPINT136_EN, R_TSPINT136_STATUS},
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};
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static void aspeed_2700tsp_intc_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
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dc->desc = "ASPEED 2700 TSP INTC Controller";
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aic->num_lines = 32;
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aic->num_inpins = 10;
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aic->num_outpins = 19;
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aic->mem_size = 0x4000;
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aic->nr_regs = 0x3B08 >> 2;
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aic->reg_offset = 0;
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aic->reg_ops = &aspeed_tsp_intc_ops;
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aic->irq_table = aspeed_2700tsp_intc_irqs;
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aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intc_irqs);
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}
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static const TypeInfo aspeed_2700tsp_intc_info = {
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.name = TYPE_ASPEED_2700TSP_INTC,
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.parent = TYPE_ASPEED_INTC,
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.class_init = aspeed_2700tsp_intc_class_init,
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};
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static AspeedINTCIRQ aspeed_2700tsp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
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{0, 0, 1, R_TSPINT160_EN, R_TSPINT160_STATUS},
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{1, 1, 1, R_TSPINT161_EN, R_TSPINT161_STATUS},
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{2, 2, 1, R_TSPINT162_EN, R_TSPINT162_STATUS},
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{3, 3, 1, R_TSPINT163_EN, R_TSPINT163_STATUS},
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{4, 4, 1, R_TSPINT164_EN, R_TSPINT164_STATUS},
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{5, 5, 1, R_TSPINT165_EN, R_TSPINT165_STATUS},
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};
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static void aspeed_2700tsp_intcio_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
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dc->desc = "ASPEED 2700 TSP INTC IO Controller";
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aic->num_lines = 32;
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aic->num_inpins = 6;
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aic->num_outpins = 6;
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aic->mem_size = 0x400;
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aic->nr_regs = 0x258 >> 2;
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aic->reg_offset = 0x0;
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aic->reg_ops = &aspeed_tsp_intcio_ops;
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aic->irq_table = aspeed_2700tsp_intcio_irqs;
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aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intcio_irqs);
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}
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static const TypeInfo aspeed_2700tsp_intcio_info = {
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.name = TYPE_ASPEED_2700TSP_INTCIO,
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.parent = TYPE_ASPEED_INTC,
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.class_init = aspeed_2700tsp_intcio_class_init,
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};
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static void aspeed_intc_register_types(void)
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{
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type_register_static(&aspeed_intc_info);
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@ -890,6 +1093,8 @@ static void aspeed_intc_register_types(void)
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type_register_static(&aspeed_2700_intcio_info);
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type_register_static(&aspeed_2700ssp_intc_info);
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type_register_static(&aspeed_2700ssp_intcio_info);
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type_register_static(&aspeed_2700tsp_intc_info);
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type_register_static(&aspeed_2700tsp_intcio_info);
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}
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type_init(aspeed_intc_register_types);
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