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hw/intc/aspeed: Add support for AST2700 SSP INTC
- Define new types for ast2700ssp INTC and INTCIO
- Add register definitions for SSP INTC and INTCIO
- Implement write handlers for SSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the SSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:
- AST2700
Support GICINT128 to GICINT136 in INTC
The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-ssp
Support SSPINT128 to SSPINT136 in INTC
The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ib8cb0e264505cef48e17f173e057f3b2d1ea35c4
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-4-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Steven Lee
Cédric Le Goater
parent
78110f821a
commit
8872b6717c
2 changed files with 214 additions and 0 deletions
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@ -62,6 +62,50 @@ REG32(GICINT196_STATUS, 0x44)
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REG32(GICINT197_EN, 0x50)
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REG32(GICINT197_STATUS, 0x54)
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/*
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* SSP INTC Registers
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*/
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REG32(SSPINT128_EN, 0x2000)
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REG32(SSPINT128_STATUS, 0x2004)
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REG32(SSPINT129_EN, 0x2100)
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REG32(SSPINT129_STATUS, 0x2104)
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REG32(SSPINT130_EN, 0x2200)
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REG32(SSPINT130_STATUS, 0x2204)
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REG32(SSPINT131_EN, 0x2300)
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REG32(SSPINT131_STATUS, 0x2304)
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REG32(SSPINT132_EN, 0x2400)
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REG32(SSPINT132_STATUS, 0x2404)
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REG32(SSPINT133_EN, 0x2500)
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REG32(SSPINT133_STATUS, 0x2504)
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REG32(SSPINT134_EN, 0x2600)
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REG32(SSPINT134_STATUS, 0x2604)
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REG32(SSPINT135_EN, 0x2700)
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REG32(SSPINT135_STATUS, 0x2704)
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REG32(SSPINT136_EN, 0x2800)
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REG32(SSPINT136_STATUS, 0x2804)
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REG32(SSPINT137_EN, 0x2900)
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REG32(SSPINT137_STATUS, 0x2904)
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REG32(SSPINT138_EN, 0x2A00)
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REG32(SSPINT138_STATUS, 0x2A04)
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REG32(SSPINT160_169_EN, 0x2B00)
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REG32(SSPINT160_169_STATUS, 0x2B04)
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/*
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* SSP INTCIO Registers
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*/
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REG32(SSPINT160_EN, 0x180)
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REG32(SSPINT160_STATUS, 0x184)
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REG32(SSPINT161_EN, 0x190)
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REG32(SSPINT161_STATUS, 0x194)
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REG32(SSPINT162_EN, 0x1A0)
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REG32(SSPINT162_STATUS, 0x1A4)
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REG32(SSPINT163_EN, 0x1B0)
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REG32(SSPINT163_STATUS, 0x1B4)
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REG32(SSPINT164_EN, 0x1C0)
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REG32(SSPINT164_STATUS, 0x1C4)
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REG32(SSPINT165_EN, 0x1D0)
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REG32(SSPINT165_STATUS, 0x1D4)
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static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
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uint32_t reg)
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{
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@ -450,6 +494,50 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
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}
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}
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static void aspeed_ssp_intc_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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AspeedINTCState *s = ASPEED_INTC(opaque);
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const char *name = object_get_typename(OBJECT(s));
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uint32_t reg = offset >> 2;
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trace_aspeed_intc_write(name, offset, size, data);
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switch (reg) {
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case R_SSPINT128_EN:
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case R_SSPINT129_EN:
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case R_SSPINT130_EN:
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case R_SSPINT131_EN:
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case R_SSPINT132_EN:
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case R_SSPINT133_EN:
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case R_SSPINT134_EN:
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case R_SSPINT135_EN:
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case R_SSPINT136_EN:
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case R_SSPINT160_169_EN:
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aspeed_intc_enable_handler(s, offset, data);
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break;
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case R_SSPINT128_STATUS:
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case R_SSPINT129_STATUS:
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case R_SSPINT130_STATUS:
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case R_SSPINT131_STATUS:
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case R_SSPINT132_STATUS:
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case R_SSPINT133_STATUS:
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case R_SSPINT134_STATUS:
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case R_SSPINT135_STATUS:
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case R_SSPINT136_STATUS:
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aspeed_intc_status_handler(s, offset, data);
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break;
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case R_SSPINT160_169_STATUS:
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aspeed_intc_status_handler_multi_outpins(s, offset, data);
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break;
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default:
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s->regs[reg] = data;
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break;
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}
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return;
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}
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static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
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unsigned int size)
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{
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@ -496,6 +584,39 @@ static void aspeed_intcio_write(void *opaque, hwaddr offset, uint64_t data,
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}
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}
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static void aspeed_ssp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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AspeedINTCState *s = ASPEED_INTC(opaque);
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const char *name = object_get_typename(OBJECT(s));
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uint32_t reg = offset >> 2;
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trace_aspeed_intc_write(name, offset, size, data);
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switch (reg) {
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case R_SSPINT160_EN:
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case R_SSPINT161_EN:
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case R_SSPINT162_EN:
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case R_SSPINT163_EN:
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case R_SSPINT164_EN:
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case R_SSPINT165_EN:
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aspeed_intc_enable_handler(s, offset, data);
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break;
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case R_SSPINT160_STATUS:
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case R_SSPINT161_STATUS:
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case R_SSPINT162_STATUS:
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case R_SSPINT163_STATUS:
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case R_SSPINT164_STATUS:
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case R_SSPINT165_STATUS:
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aspeed_intc_status_handler(s, offset, data);
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break;
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default:
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s->regs[reg] = data;
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break;
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}
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return;
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}
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static const MemoryRegionOps aspeed_intc_ops = {
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.read = aspeed_intc_read,
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@ -517,6 +638,26 @@ static const MemoryRegionOps aspeed_intcio_ops = {
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}
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};
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static const MemoryRegionOps aspeed_ssp_intc_ops = {
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.read = aspeed_intc_read,
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.write = aspeed_ssp_intc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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}
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};
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static const MemoryRegionOps aspeed_ssp_intcio_ops = {
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.read = aspeed_intcio_read,
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.write = aspeed_ssp_intcio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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}
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};
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static void aspeed_intc_instance_init(Object *obj)
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{
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AspeedINTCState *s = ASPEED_INTC(obj);
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@ -674,11 +815,81 @@ static const TypeInfo aspeed_2700_intcio_info = {
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.class_init = aspeed_2700_intcio_class_init,
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};
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static AspeedINTCIRQ aspeed_2700ssp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
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{0, 0, 10, R_SSPINT160_169_EN, R_SSPINT160_169_STATUS},
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{1, 10, 1, R_SSPINT128_EN, R_SSPINT128_STATUS},
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{2, 11, 1, R_SSPINT129_EN, R_SSPINT129_STATUS},
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{3, 12, 1, R_SSPINT130_EN, R_SSPINT130_STATUS},
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{4, 13, 1, R_SSPINT131_EN, R_SSPINT131_STATUS},
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{5, 14, 1, R_SSPINT132_EN, R_SSPINT132_STATUS},
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{6, 15, 1, R_SSPINT133_EN, R_SSPINT133_STATUS},
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{7, 16, 1, R_SSPINT134_EN, R_SSPINT134_STATUS},
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{8, 17, 1, R_SSPINT135_EN, R_SSPINT135_STATUS},
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{9, 18, 1, R_SSPINT136_EN, R_SSPINT136_STATUS},
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};
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static void aspeed_2700ssp_intc_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
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dc->desc = "ASPEED 2700 SSP INTC Controller";
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aic->num_lines = 32;
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aic->num_inpins = 10;
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aic->num_outpins = 19;
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aic->mem_size = 0x4000;
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aic->nr_regs = 0x2B08 >> 2;
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aic->reg_offset = 0x0;
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aic->reg_ops = &aspeed_ssp_intc_ops;
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aic->irq_table = aspeed_2700ssp_intc_irqs;
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aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intc_irqs);
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}
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static const TypeInfo aspeed_2700ssp_intc_info = {
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.name = TYPE_ASPEED_2700SSP_INTC,
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.parent = TYPE_ASPEED_INTC,
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.class_init = aspeed_2700ssp_intc_class_init,
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};
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static AspeedINTCIRQ aspeed_2700ssp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
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{0, 0, 1, R_SSPINT160_EN, R_SSPINT160_STATUS},
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{1, 1, 1, R_SSPINT161_EN, R_SSPINT161_STATUS},
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{2, 2, 1, R_SSPINT162_EN, R_SSPINT162_STATUS},
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{3, 3, 1, R_SSPINT163_EN, R_SSPINT163_STATUS},
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{4, 4, 1, R_SSPINT164_EN, R_SSPINT164_STATUS},
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{5, 5, 1, R_SSPINT165_EN, R_SSPINT165_STATUS},
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};
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static void aspeed_2700ssp_intcio_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
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dc->desc = "ASPEED 2700 SSP INTC IO Controller";
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aic->num_lines = 32;
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aic->num_inpins = 6;
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aic->num_outpins = 6;
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aic->mem_size = 0x400;
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aic->nr_regs = 0x1d8 >> 2;
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aic->reg_offset = 0;
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aic->reg_ops = &aspeed_ssp_intcio_ops;
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aic->irq_table = aspeed_2700ssp_intcio_irqs;
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aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intcio_irqs);
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}
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static const TypeInfo aspeed_2700ssp_intcio_info = {
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.name = TYPE_ASPEED_2700SSP_INTCIO,
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.parent = TYPE_ASPEED_INTC,
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.class_init = aspeed_2700ssp_intcio_class_init,
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};
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static void aspeed_intc_register_types(void)
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{
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type_register_static(&aspeed_intc_info);
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type_register_static(&aspeed_2700_intc_info);
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type_register_static(&aspeed_2700_intcio_info);
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type_register_static(&aspeed_2700ssp_intc_info);
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type_register_static(&aspeed_2700ssp_intcio_info);
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}
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type_init(aspeed_intc_register_types);
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@ -15,6 +15,9 @@
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#define TYPE_ASPEED_INTC "aspeed.intc"
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#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
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#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
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#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
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#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
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OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
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#define ASPEED_INTC_MAX_INPINS 10
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