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tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}

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Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two
inputs or outputs are required. This simplifies the processing of
i64/i128 depending on host word size.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-09 12:55:15 -08:00
parent 33aba058c8
commit aae2456ac0
15 changed files with 200 additions and 306 deletions
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16
tcg/arm/tcg-target.c.inc
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@ -2570,17 +2570,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const int const_args[TCG_MAX_OP_ARGS])
{
switch (opc) {
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld:
tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_ld2:
tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st:
tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_i64:
case INDEX_op_qemu_st2:
tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
break;
@ -2596,13 +2596,13 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld:
return C_O1_I1(r, q);
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_ld2:
return C_O2_I1(e, p, q);
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st:
return C_O0_I2(q, q);
case INDEX_op_qemu_st_i64:
case INDEX_op_qemu_st2:
return C_O0_I3(Q, p, q);
case INDEX_op_st_vec: