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hw/cxl/cxl-mailbox-utils: CXL CCI Get/Set alert config commands

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1) get alert configuration(Opcode 4201h)
2) set alert configuration(Opcode 4202h)

Signed-off-by: Sweta Kumari <s5.kumari@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20250305092501.191929-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Sweta Kumari 2025-03-05 09:24:57 +00:00 • committed by Michael S. Tsirkin
parent 40ab4ed107
commit a3e0b1ff37
3 changed files with 134 additions and 0 deletions
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105
hw/cxl/cxl-mailbox-utils.c
View file

@ -28,6 +28,11 @@
#define CXL_DC_EVENT_LOG_SIZE 8
#define CXL_NUM_EXTENTS_SUPPORTED 512
#define CXL_NUM_TAGS_SUPPORTED 0
#define CXL_ALERTS_LIFE_USED_WARN_THRESH (1 << 0)
#define CXL_ALERTS_OVER_TEMP_WARN_THRESH (1 << 1)
#define CXL_ALERTS_UNDER_TEMP_WARN_THRESH (1 << 2)
#define CXL_ALERTS_COR_VMEM_ERR_WARN_THRESH (1 << 3)
#define CXL_ALERTS_COR_PMEM_ERR_WARN_THRESH (1 << 4)
/*
* How to add a new command, example. The command set FOO, with cmd BAR.
@ -86,6 +91,9 @@ enum {
#define GET_PARTITION_INFO 0x0
#define GET_LSA 0x2
#define SET_LSA 0x3
HEALTH_INFO_ALERTS = 0x42,
#define GET_ALERT_CONFIG 0x1
#define SET_ALERT_CONFIG 0x2
SANITIZE = 0x44,
#define OVERWRITE 0x0
#define SECURE_ERASE 0x1
@ -1610,6 +1618,97 @@ static CXLRetCode cmd_ccls_set_lsa(const struct cxl_cmd *cmd,
return CXL_MBOX_SUCCESS;
}
/* CXL r3.2 Section 8.2.10.9.3.2 Get Alert Configuration (Opcode 4201h) */
static CXLRetCode cmd_get_alert_config(const struct cxl_cmd *cmd,
uint8_t *payload_in,
size_t len_in,
uint8_t *payload_out,
size_t *len_out,
CXLCCI *cci)
{
CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
CXLAlertConfig *out = (CXLAlertConfig *)payload_out;
memcpy(out, &ct3d->alert_config, sizeof(ct3d->alert_config));
*len_out = sizeof(ct3d->alert_config);
return CXL_MBOX_SUCCESS;
}
/* CXL r3.2 Section 8.2.10.9.3.3 Set Alert Configuration (Opcode 4202h) */
static CXLRetCode cmd_set_alert_config(const struct cxl_cmd *cmd,
uint8_t *payload_in,
size_t len_in,
uint8_t *payload_out,
size_t *len_out,
CXLCCI *cci)
{
CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
CXLAlertConfig *alert_config = &ct3d->alert_config;
struct {
uint8_t valid_alert_actions;
uint8_t enable_alert_actions;
uint8_t life_used_warn_thresh;
uint8_t rsvd;
uint16_t over_temp_warn_thresh;
uint16_t under_temp_warn_thresh;
uint16_t cor_vmem_err_warn_thresh;
uint16_t cor_pmem_err_warn_thresh;
} QEMU_PACKED *in = (void *)payload_in;
if (in->valid_alert_actions & CXL_ALERTS_LIFE_USED_WARN_THRESH) {
/*
* CXL r3.2 Table 8-149 The life used warning threshold shall be
* less than the life used critical alert value.
*/
if (in->life_used_warn_thresh >=
alert_config->life_used_crit_alert_thresh) {
return CXL_MBOX_INVALID_INPUT;
}
alert_config->life_used_warn_thresh = in->life_used_warn_thresh;
alert_config->enable_alerts |= CXL_ALERTS_LIFE_USED_WARN_THRESH;
}
if (in->valid_alert_actions & CXL_ALERTS_OVER_TEMP_WARN_THRESH) {
/*
* CXL r3.2 Table 8-149 The Device Over-Temperature Warning Threshold
* shall be less than the the Device Over-Temperature Critical
* Alert Threshold.
*/
if (in->over_temp_warn_thresh >=
alert_config->over_temp_crit_alert_thresh) {
return CXL_MBOX_INVALID_INPUT;
}
alert_config->over_temp_warn_thresh = in->over_temp_warn_thresh;
alert_config->enable_alerts |= CXL_ALERTS_OVER_TEMP_WARN_THRESH;
}
if (in->valid_alert_actions & CXL_ALERTS_UNDER_TEMP_WARN_THRESH) {
/*
* CXL r3.2 Table 8-149 The Device Under-Temperature Warning Threshold
* shall be higher than the the Device Under-Temperature Critical
* Alert Threshold.
*/
if (in->under_temp_warn_thresh <=
alert_config->under_temp_crit_alert_thresh) {
return CXL_MBOX_INVALID_INPUT;
}
alert_config->under_temp_warn_thresh = in->under_temp_warn_thresh;
alert_config->enable_alerts |= CXL_ALERTS_UNDER_TEMP_WARN_THRESH;
}
if (in->valid_alert_actions & CXL_ALERTS_COR_VMEM_ERR_WARN_THRESH) {
alert_config->cor_vmem_err_warn_thresh = in->cor_vmem_err_warn_thresh;
alert_config->enable_alerts |= CXL_ALERTS_COR_VMEM_ERR_WARN_THRESH;
}
if (in->valid_alert_actions & CXL_ALERTS_COR_PMEM_ERR_WARN_THRESH) {
alert_config->cor_pmem_err_warn_thresh = in->cor_pmem_err_warn_thresh;
alert_config->enable_alerts |= CXL_ALERTS_COR_PMEM_ERR_WARN_THRESH;
}
return CXL_MBOX_SUCCESS;
}
/* Perform the actual device zeroing */
static void __do_sanitization(CXLType3Dev *ct3d)
{
@ -3173,6 +3272,12 @@ static const struct cxl_cmd cxl_cmd_set[256][256] = {
[CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 8, 0 },
[CCLS][SET_LSA] = { "CCLS_SET_LSA", cmd_ccls_set_lsa,
~0, CXL_MBOX_IMMEDIATE_CONFIG_CHANGE | CXL_MBOX_IMMEDIATE_DATA_CHANGE },
[HEALTH_INFO_ALERTS][GET_ALERT_CONFIG] = {
"HEALTH_INFO_ALERTS_GET_ALERT_CONFIG",
cmd_get_alert_config, 0, 0 },
[HEALTH_INFO_ALERTS][SET_ALERT_CONFIG] = {
"HEALTH_INFO_ALERTS_SET_ALERT_CONFIG",
cmd_set_alert_config, 12, CXL_MBOX_IMMEDIATE_POLICY_CHANGE },
[SANITIZE][OVERWRITE] = { "SANITIZE_OVERWRITE", cmd_sanitize_overwrite, 0,
(CXL_MBOX_IMMEDIATE_DATA_CHANGE |
CXL_MBOX_SECURITY_STATE_CHANGE |

14
hw/mem/cxl_type3.c
View file

@ -843,6 +843,19 @@ static DOEProtocol doe_cdat_prot[] = {
{ }
};
/* Initialize CXL device alerts with default threshold values. */
static void init_alert_config(CXLType3Dev *ct3d)
{
ct3d->alert_config = (CXLAlertConfig) {
.life_used_crit_alert_thresh = 75,
.life_used_warn_thresh = 40,
.over_temp_crit_alert_thresh = 35,
.under_temp_crit_alert_thresh = 10,
.over_temp_warn_thresh = 25,
.under_temp_warn_thresh = 20
};
}
static void ct3_realize(PCIDevice *pci_dev, Error **errp)
{
ERRP_GUARD();
@ -910,6 +923,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
goto err_msix_uninit;
}
init_alert_config(ct3d);
pcie_cap_deverr_init(pci_dev);
/* Leave a bit of room for expansion */
rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, errp);

15
include/hw/cxl/cxl_device.h
View file

@ -542,6 +542,19 @@ typedef struct CXLSetFeatureInfo {
struct CXLSanitizeInfo;
typedef struct CXLAlertConfig {
uint8_t valid_alerts;
uint8_t enable_alerts;
uint8_t life_used_crit_alert_thresh;
uint8_t life_used_warn_thresh;
uint16_t over_temp_crit_alert_thresh;
uint16_t under_temp_crit_alert_thresh;
uint16_t over_temp_warn_thresh;
uint16_t under_temp_warn_thresh;
uint16_t cor_vmem_err_warn_thresh;
uint16_t cor_pmem_err_warn_thresh;
} QEMU_PACKED CXLAlertConfig;
struct CXLType3Dev {
/* Private */
PCIDevice parent_obj;
@ -563,6 +576,8 @@ struct CXLType3Dev {
CXLCCI vdm_fm_owned_ld_mctp_cci;
CXLCCI ld0_cci;
CXLAlertConfig alert_config;
/* PCIe link characteristics */
PCIExpLinkSpeed speed;
PCIExpLinkWidth width;