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hw/net/xilinx_ethlite: Map TX_CTRL as MMIO

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Add TX_CTRL to the TX registers MMIO region.

The memory flat view becomes:

  (qemu) info mtree -f
  FlatView #0
   Root memory region: system
    0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
    00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio
    00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io
    0000000081000800-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000800
    0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io
    0000000081001000-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001000
    00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io
    0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800
    0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-19-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-11-11 17:19:39 +01:00
parent 01198add29
commit a34606dbb3
1 changed files with 24 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

54
hw/net/xilinx_ethlite.c
View file

@ -42,10 +42,8 @@
#define BUFSZ_MAX 0x07e4
#define A_MDIO_BASE 0x07e4
#define A_TX_BASE0 0x07f4
#define R_TX_CTRL0 (0x07fc / 4)
#define R_TX_BUF1 (0x0800 / 4)
#define A_TX_BASE1 0x0ff4
#define R_TX_CTRL1 (0x0ffc / 4)
#define R_RX_BUF0 (0x1000 / 4)
#define A_RX_BASE0 0x17fc
@ -56,6 +54,7 @@
enum {
TX_LEN = 0,
TX_GIE = 1,
TX_CTRL = 2,
TX_MAX
};
@ -144,6 +143,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size)
case TX_GIE:
r = s->port[port_index].reg.tx_gie;
break;
case TX_CTRL:
r = s->port[port_index].reg.tx_ctrl;
break;
default:
g_assert_not_reached();
}
@ -164,6 +166,26 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
case TX_GIE:
s->port[port_index].reg.tx_gie = value;
break;
case TX_CTRL:
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
txbuf_ptr(s, port_index),
s->port[port_index].reg.tx_len);
if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
eth_pulse_irq(s);
}
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6);
if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
eth_pulse_irq(s);
}
}
/*
* We are fast and get ready pretty much immediately
* so we actually never flip the S nor P bits to one.
*/
s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S);
break;
default:
g_assert_not_reached();
}
@ -236,18 +258,12 @@ static uint64_t
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
XlnxXpsEthLite *s = opaque;
unsigned port_index = addr_to_port_index(addr);
uint32_t r = 0;
addr >>= 2;
switch (addr)
{
case R_TX_CTRL1:
case R_TX_CTRL0:
r = s->port[port_index].reg.tx_ctrl;
break;
default:
r = tswap32(s->regs[addr]);
break;
@ -260,33 +276,11 @@ eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
XlnxXpsEthLite *s = opaque;
unsigned int port_index = addr_to_port_index(addr);
uint32_t value = val64;
addr >>= 2;
switch (addr)
{
case R_TX_CTRL0:
case R_TX_CTRL1:
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
txbuf_ptr(s, port_index),
s->port[port_index].reg.tx_len);
if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
eth_pulse_irq(s);
}
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6);
if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
eth_pulse_irq(s);
}
}
/* We are fast and get ready pretty much immediately so
we actually never flip the S nor P bits to one. */
s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S);
break;
default:
s->regs[addr] = tswap32(value);
break;