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hw/net/xilinx_ethlite: Map TX_GIE as MMIO

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Add TX_GIE to the TX registers MMIO region.

Before TX_GIE1 was accessed as RAM, with no effect.
Now it is accessed as MMIO, also without any effect.

The memory flat view becomes:

  (qemu) info mtree -f
  FlatView #0
   Root memory region: system
    0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
    00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio
    00000000810007f4-00000000810007fb (prio 0, i/o): ethlite.tx[0]io
    00000000810007fc-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007fc
    0000000081000ff4-0000000081000ffb (prio 0, i/o): ethlite.tx[1]io
    0000000081000ffc-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ffc
    00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io
    0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800
    0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-18-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-11-11 17:15:56 +01:00
parent 46dd6af259
commit 01198add29
1 changed files with 7 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

17
hw/net/xilinx_ethlite.c
View file

@ -42,7 +42,6 @@
#define BUFSZ_MAX 0x07e4
#define A_MDIO_BASE 0x07e4
#define A_TX_BASE0 0x07f4
#define R_TX_GIE0 (0x07f8 / 4)
#define R_TX_CTRL0 (0x07fc / 4)
#define R_TX_BUF1 (0x0800 / 4)
#define A_TX_BASE1 0x0ff4
@ -56,6 +55,7 @@
enum {
TX_LEN = 0,
TX_GIE = 1,
TX_MAX
};
@ -141,6 +141,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size)
case TX_LEN:
r = s->port[port_index].reg.tx_len;
break;
case TX_GIE:
r = s->port[port_index].reg.tx_gie;
break;
default:
g_assert_not_reached();
}
@ -158,6 +161,9 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
case TX_LEN:
s->port[port_index].reg.tx_len = value;
break;
case TX_GIE:
s->port[port_index].reg.tx_gie = value;
break;
default:
g_assert_not_reached();
}
@ -237,10 +243,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
switch (addr)
{
case R_TX_GIE0:
r = s->port[port_index].reg.tx_gie;
break;
case R_TX_CTRL1:
case R_TX_CTRL0:
r = s->port[port_index].reg.tx_ctrl;
@ -285,11 +287,6 @@ eth_write(void *opaque, hwaddr addr,
s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S);
break;
/* Keep these native. */
case R_TX_GIE0:
s->port[port_index].reg.tx_gie = value;
break;
default:
s->regs[addr] = tswap32(value);
break;