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tcg: Drop support for two address registers in gen_ldst

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-04 11:06:26 -08:00
parent f441b4d19b
commit a0ecb8e494
2 changed files with 4 additions and 21 deletions
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21
tcg/tcg-op-ldst.c
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@ -91,25 +91,10 @@ static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
static void gen_ldst(TCGOpcode opc, TCGType type, TCGTemp *vl, TCGTemp *vh, static void gen_ldst(TCGOpcode opc, TCGType type, TCGTemp *vl, TCGTemp *vh,
TCGTemp *addr, MemOpIdx oi) TCGTemp *addr, MemOpIdx oi)
{ {
if (TCG_TARGET_REG_BITS == 64 || tcg_ctx->addr_type == TCG_TYPE_I32) { if (vh) {
if (vh) { tcg_gen_op4(opc, type, temp_arg(vl), temp_arg(vh), temp_arg(addr), oi);
tcg_gen_op4(opc, type, temp_arg(vl), temp_arg(vh),
temp_arg(addr), oi);
} else {
tcg_gen_op3(opc, type, temp_arg(vl), temp_arg(addr), oi);
}
} else { } else {
/* See TCGV_LOW/HIGH. */ tcg_gen_op3(opc, type, temp_arg(vl), temp_arg(addr), oi);
TCGTemp *al = addr + HOST_BIG_ENDIAN;
TCGTemp *ah = addr + !HOST_BIG_ENDIAN;
if (vh) {
tcg_gen_op5(opc, type, temp_arg(vl), temp_arg(vh),
temp_arg(al), temp_arg(ah), oi);
} else {
tcg_gen_op4(opc, type, temp_arg(vl),
temp_arg(al), temp_arg(ah), oi);
}
} }
} }

4
tcg/tcg.c
View file

@ -1690,9 +1690,7 @@ void tcg_func_start(TCGContext *s)
s->emit_before_op = NULL; s->emit_before_op = NULL;
QSIMPLEQ_INIT(&s->labels); QSIMPLEQ_INIT(&s->labels);
tcg_debug_assert(s->addr_type == TCG_TYPE_I32 || tcg_debug_assert(s->addr_type <= TCG_TYPE_REG);
s->addr_type == TCG_TYPE_I64);
tcg_debug_assert(s->insn_start_words > 0); tcg_debug_assert(s->insn_start_words > 0);
} }