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tcg: Remove TCG_OVERSIZED_GUEST
This is now prohibited in configuration. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
3a3b282879
commit
f441b4d19b
7 changed files with 8 additions and 97 deletions
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@ -47,7 +47,6 @@
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#include "qemu/plugin-memory.h"
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#endif
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#include "tcg/tcg-ldst.h"
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#include "tcg/oversized-guest.h"
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/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
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/* #define DEBUG_TLB */
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@ -118,12 +117,8 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
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return qatomic_read(ptr);
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#else
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const uint64_t *ptr = &entry->addr_idx[access_type];
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# if TCG_OVERSIZED_GUEST
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return *ptr;
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# else
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/* ofs might correspond to .addr_write, so use qatomic_read */
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return qatomic_read(ptr);
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# endif
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#endif
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}
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@ -908,8 +903,6 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
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uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
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ptr_write += HOST_BIG_ENDIAN;
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qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
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#elif TCG_OVERSIZED_GUEST
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tlb_entry->addr_write |= TLB_NOTDIRTY;
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#else
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qatomic_set(&tlb_entry->addr_write,
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tlb_entry->addr_write | TLB_NOTDIRTY);
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@ -28,7 +28,6 @@
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#include "exec/replay-core.h"
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#include "system/cpu-timers.h"
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#include "tcg/startup.h"
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#include "tcg/oversized-guest.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/accel.h"
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@ -41,6 +40,8 @@
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#include "hw/boards.h"
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#endif
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#include "internal-common.h"
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#include "cpu-param.h"
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struct TCGState {
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AccelState parent_obj;
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@ -72,7 +73,7 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
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static bool default_mttcg_enabled(void)
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{
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if (icount_enabled() || TCG_OVERSIZED_GUEST) {
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if (icount_enabled()) {
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return false;
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}
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#ifdef TARGET_SUPPORTS_MTTCG
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@ -145,9 +146,7 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp)
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TCGState *s = TCG_STATE(obj);
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if (strcmp(value, "multi") == 0) {
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if (TCG_OVERSIZED_GUEST) {
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error_setg(errp, "No MTTCG when guest word size > hosts");
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} else if (icount_enabled()) {
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if (icount_enabled()) {
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error_setg(errp, "No MTTCG when icount is enabled");
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} else {
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#ifndef TARGET_SUPPORTS_MTTCG
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@ -37,7 +37,6 @@ if:
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* forced by --accel tcg,thread=single
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* enabling --icount mode
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* 64 bit guests on 32 bit hosts (TCG_OVERSIZED_GUEST)
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In the general case of running translated code there should be no
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inter-vCPU dependencies and all vCPUs should be able to run at full
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@ -56,25 +56,13 @@
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*/
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#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST)
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/* Sanity check that the size of an atomic operation isn't "overly large".
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/*
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* Sanity check that the size of an atomic operation isn't "overly large".
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* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
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* want to use them because we ought not need them, and this lets us do a
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* bit of sanity checking that other 32-bit hosts might build.
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*
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* That said, we have a problem on 64-bit ILP32 hosts in that in order to
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* sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
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* We'd prefer not want to pull in everything else TCG related, so handle
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* those few cases by hand.
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*
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* Note that x32 is fully detected with __x86_64__ + _ILP32, and that for
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* Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &
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* n64 (LP64) ABIs are both detected using __mips64.
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*/
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#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)
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# define ATOMIC_REG_SIZE 8
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#else
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# define ATOMIC_REG_SIZE sizeof(void *)
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#endif
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#define ATOMIC_REG_SIZE sizeof(void *)
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/* Weak atomic operations prevent the compiler moving other
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* loads/stores past the atomic operation load/store. However there is
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@ -1,23 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define TCG_OVERSIZED_GUEST
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* Copyright (c) 2008 Fabrice Bellard
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*/
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#ifndef EXEC_TCG_OVERSIZED_GUEST_H
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#define EXEC_TCG_OVERSIZED_GUEST_H
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#include "tcg-target-reg-bits.h"
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#include "cpu-param.h"
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/*
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* Oversized TCG guests make things like MTTCG hard
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* as we can't use atomics for cputlb updates.
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*/
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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#define TCG_OVERSIZED_GUEST 1
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#else
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#define TCG_OVERSIZED_GUEST 0
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#endif
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#endif
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@ -16,9 +16,6 @@
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#include "internals.h"
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#include "cpu-features.h"
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#include "idau.h"
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#ifdef CONFIG_TCG
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# include "tcg/oversized-guest.h"
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#endif
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typedef struct S1Translate {
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/*
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@ -840,7 +837,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
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ptw->out_rw = true;
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}
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#ifdef CONFIG_ATOMIC64
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if (ptw->out_be) {
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old_val = cpu_to_be64(old_val);
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new_val = cpu_to_be64(new_val);
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@ -852,36 +848,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
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cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val);
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cur_val = le64_to_cpu(cur_val);
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}
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#else
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/*
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* We can't support the full 64-bit atomic cmpxchg on the host.
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* Because this is only used for FEAT_HAFDBS, which is only for AA64,
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* we know that TCG_OVERSIZED_GUEST is set, which means that we are
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* running in round-robin mode and could only race with dma i/o.
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*/
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#if !TCG_OVERSIZED_GUEST
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# error "Unexpected configuration"
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#endif
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bool locked = bql_locked();
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if (!locked) {
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bql_lock();
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}
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if (ptw->out_be) {
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cur_val = ldq_be_p(host);
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if (cur_val == old_val) {
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stq_be_p(host, new_val);
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}
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} else {
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cur_val = ldq_le_p(host);
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if (cur_val == old_val) {
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stq_le_p(host, new_val);
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}
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}
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if (!locked) {
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bql_unlock();
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}
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#endif
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return cur_val;
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#else
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/* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */
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@ -32,7 +32,6 @@
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#include "system/cpu-timers.h"
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#include "cpu_bits.h"
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#include "debug.h"
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#include "tcg/oversized-guest.h"
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#include "pmp.h"
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int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
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@ -1167,9 +1166,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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hwaddr pte_addr;
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int i;
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#if !TCG_OVERSIZED_GUEST
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restart:
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#endif
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restart:
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for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
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target_ulong idx;
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if (i == 0) {
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@ -1388,13 +1385,6 @@ restart:
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false, MEMTXATTRS_UNSPECIFIED);
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if (memory_region_is_ram(mr)) {
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target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
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#if TCG_OVERSIZED_GUEST
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/*
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* MTTCG is not enabled on oversized TCG guests so
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* page table updates do not need to be atomic
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*/
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*pte_pa = pte = updated_pte;
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#else
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target_ulong old_pte;
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if (riscv_cpu_sxl(env) == MXL_RV32) {
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old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
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goto restart;
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}
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pte = updated_pte;
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#endif
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} else {
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/*
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* Misconfigured PTE in ROM (AD bits are not preset) or
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