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{hw/i2c,docs/system/arm}: Allwinner TWI/I2C Emulation

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This patch implements Allwinner TWI/I2C controller emulation. Only
master-mode functionality is implemented.

The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is
first part enabling the TWI/I2C bus operation.

Since both Allwinner A10 and H3 use the same module, it is added for
both boards.

Docs are also updated for Cubieboard and Orangepi-PC board to indicate
I2C availability.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20221226220303.14420-4-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Strahinja Jankovic 2022-12-26 23:02:59 +01:00 • committed by Peter Maydell
parent edd3a59d5b
commit 9be8a82c0e
12 changed files with 551 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/hw/arm/allwinner-a10.h
View file

@ -15,6 +15,7 @@
#include "hw/rtc/allwinner-rtc.h"
#include "hw/misc/allwinner-a10-ccm.h"
#include "hw/misc/allwinner-a10-dramc.h"
#include "hw/i2c/allwinner-i2c.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
@ -40,6 +41,7 @@ struct AwA10State {
AwEmacState emac;
AllwinnerAHCIState sata;
AwSdHostState mmc0;
AWI2CState i2c0;
AwRtcState rtc;
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];

3
include/hw/arm/allwinner-h3.h
View file

@ -47,6 +47,7 @@
#include "hw/sd/allwinner-sdhost.h"
#include "hw/net/allwinner-sun8i-emac.h"
#include "hw/rtc/allwinner-rtc.h"
#include "hw/i2c/allwinner-i2c.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@ -82,6 +83,7 @@ enum {
AW_H3_DEV_UART2,
AW_H3_DEV_UART3,
AW_H3_DEV_EMAC,
AW_H3_DEV_TWI0,
AW_H3_DEV_DRAMCOM,
AW_H3_DEV_DRAMCTL,
AW_H3_DEV_DRAMPHY,
@ -130,6 +132,7 @@ struct AwH3State {
AwH3SysCtrlState sysctrl;
AwSidState sid;
AwSdHostState mmc0;
AWI2CState i2c0;
AwSun8iEmacState emac;
AwRtcState rtc;
GICState gic;

55
include/hw/i2c/allwinner-i2c.h Normal file
View file

@ -0,0 +1,55 @@
/*
* Allwinner I2C Bus Serial Interface registers definition
*
* Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
*
* This file is derived from IMX I2C controller,
* by Jean-Christophe DUBOIS .
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef ALLWINNER_I2C_H
#define ALLWINNER_I2C_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_AW_I2C "allwinner.i2c"
OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
#define AW_I2C_MEM_SIZE 0x24
struct AWI2CState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
I2CBus *bus;
qemu_irq irq;
uint8_t addr;
uint8_t xaddr;
uint8_t data;
uint8_t cntr;
uint8_t stat;
uint8_t ccr;
uint8_t srst;
uint8_t efr;
uint8_t lcr;
};
#endif /* ALLWINNER_I2C_H */