motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 16:23:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg: Merge INDEX_op_bswap32_{i32,i64}

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-10 19:53:51 -08:00
parent d7b15a25a7
commit 7498d882cb
7 changed files with 20 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

13
docs/devel/tcg-ops.rst
View file

@ -425,16 +425,15 @@ Misc
|
| If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value.
* - bswap32_i64 *t0*, *t1*, *flags*
* - bswap32 *t0*, *t1*, *flags*
- | 32 bit byte swap on a 64-bit value. The flags are the same as for bswap16,
except they apply from bit 31 instead of bit 15.
- | 32 bit byte swap. The flags are the same as for bswap16, except
they apply from bit 31 instead of bit 15. On TCG_TYPE_I32, the
flags should be zero.
* - bswap32_i32 *t0*, *t1*, *flags*
* - bswap64_i64 *t0*, *t1*, *flags*
bswap64_i64 *t0*, *t1*, *flags*
- | 32/64 bit byte swap. The flags are ignored, but still present
- | 64 bit byte swap. The flags are ignored, but still present
for consistency with the other bswap opcodes.
* - discard_i32/i64 *t0*

4
include/tcg/tcg-opc.h
View file

@ -44,6 +44,7 @@ DEF(add, 1, 2, 0, TCG_OPF_INT)
DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
DEF(clz, 1, 2, 0, TCG_OPF_INT)
DEF(ctpop, 1, 1, 0, TCG_OPF_INT)
DEF(ctz, 1, 2, 0, TCG_OPF_INT)
@ -96,8 +97,6 @@ DEF(sub2_i32, 2, 4, 0, 0)
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
DEF(setcond2_i32, 1, 4, 1, 0)
DEF(bswap32_i32, 1, 1, 1, 0)
/* load/store */
DEF(ld8u_i64, 1, 1, 1, 0)
DEF(ld8s_i64, 1, 1, 1, 0)
@ -122,7 +121,6 @@ DEF(extu_i32_i64, 1, 1, 0, 0)
DEF(extrl_i64_i32, 1, 1, 0, 0)
DEF(extrh_i64_i32, 1, 1, 0, 0)
DEF(bswap32_i64, 1, 1, 1, 0)
DEF(bswap64_i64, 1, 1, 1, 0)
DEF(add2_i64, 2, 4, 0, 0)

7
tcg/optimize.c
View file

@ -522,7 +522,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
x = bswap16(x);
return y & TCG_BSWAP_OS ? (int16_t)x : x;
CASE_OP_32_64(bswap32):
case INDEX_op_bswap32:
x = bswap32(x);
return y & TCG_BSWAP_OS ? (int32_t)x : x;
@ -1576,8 +1576,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
z_mask = bswap16(z_mask);
sign = INT16_MIN;
break;
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap32:
z_mask = bswap32(z_mask);
sign = INT32_MIN;
break;
@ -2870,7 +2869,7 @@ void tcg_optimize(TCGContext *s)
done = fold_brcond2(&ctx, op);
break;
case INDEX_op_bswap16:
CASE_OP_32_64(bswap32):
case INDEX_op_bswap32:
case INDEX_op_bswap64_i64:
done = fold_bswap(&ctx, op);
break;

8
tcg/tcg-op.c
View file

@ -1294,8 +1294,8 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags)
*/
void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
{
if (tcg_op_supported(INDEX_op_bswap32_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3i_i32(INDEX_op_bswap32_i32, ret, arg, 0);
if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I32, 0)) {
tcg_gen_op3i_i32(INDEX_op_bswap32, ret, arg, 0);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
TCGv_i32 t1 = tcg_temp_ebb_new_i32();
@ -2137,8 +2137,8 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
} else {
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}
} else if (tcg_op_supported(INDEX_op_bswap32_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg, flags);
} else if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I64, 0)) {
tcg_gen_op3i_i64(INDEX_op_bswap32, ret, arg, flags);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 t1 = tcg_temp_ebb_new_i64();

9
tcg/tcg.c
View file

@ -1076,8 +1076,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_brcond, TCGOutOpBrcond, outop_brcond),
OUTOP(INDEX_op_bswap16, TCGOutOpBswap, outop_bswap16),
OUTOP(INDEX_op_bswap32_i32, TCGOutOpBswap, outop_bswap32),
OUTOP(INDEX_op_bswap32_i64, TCGOutOpBswap, outop_bswap32),
OUTOP(INDEX_op_bswap32, TCGOutOpBswap, outop_bswap32),
OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz),
OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop),
OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz),
@ -2939,8 +2938,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
}
break;
case INDEX_op_bswap16:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap32:
case INDEX_op_bswap64_i64:
{
TCGArg flags = op->args[k];
@ -5486,8 +5484,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
break;
case INDEX_op_bswap16:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap32:
{
const TCGOutOpBswap *out =
container_of(all_outop[op->opc], TCGOutOpBswap, base);

5
tcg/tci.c
View file

@ -690,7 +690,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap16(regs[r1]);
break;
CASE_32_64(bswap32)
case INDEX_op_bswap32:
tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap32(regs[r1]);
break;
@ -1004,14 +1004,13 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
break;
case INDEX_op_bswap16:
case INDEX_op_bswap32:
case INDEX_op_ctpop:
case INDEX_op_mov:
case INDEX_op_neg:
case INDEX_op_not:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s, %s",

2
tcg/tci/tcg-target.c.inc
View file

@ -917,7 +917,7 @@ static const TCGOutOpBswap outop_bswap16 = {
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, unsigned flags)
{
tcg_out_op_rr(s, INDEX_op_bswap32_i32, a0, a1);
tcg_out_op_rr(s, INDEX_op_bswap32, a0, a1);
if (flags & TCG_BSWAP_OS) {
tcg_out_sextract(s, TCG_TYPE_REG, a0, a0, 0, 32);
}