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tcg: Convert bswap32 to TCGOutOpBswap

Browse source 
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-10 19:49:20 -08:00
parent 0dd07ee112
commit d7b15a25a7
24 changed files with 182 additions and 187 deletions
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2
tcg/aarch64/tcg-target-has.h
View file

@ -13,14 +13,12 @@
#define have_lse2 (cpuinfo & CPUINFO_LSE2)
/* optional instructions */
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_add2_i64 1

25
tcg/aarch64/tcg-target.c.inc
View file

@ -2456,6 +2456,20 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, unsigned flags)
{
tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
if (flags & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_XZR, a1);
@ -2626,15 +2640,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
case INDEX_op_bswap64_i64:
tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
break;
case INDEX_op_bswap32_i64:
tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
if (a2 & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
}
break;
case INDEX_op_bswap32_i32:
tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
break;
case INDEX_op_deposit_i64:
case INDEX_op_deposit_i32:
@ -3154,8 +3159,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:

1
tcg/arm/tcg-target-has.h
View file

@ -24,7 +24,6 @@ extern bool use_neon_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0

23
tcg/arm/tcg-target.c.inc
View file

@ -969,12 +969,6 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn)
g_assert_not_reached();
}
static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn)
{
/* rev */
tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
}
static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd,
TCGArg a1, int ofs, int len, bool const_a1)
{
@ -2157,6 +2151,18 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg rd, TCGReg rn, unsigned flags)
{
/* rev */
tcg_out32(s, 0x06bf0f30 | (COND_AL << 28) | (rd << 12) | rn);
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_subfi(s, type, a0, 0, a1);
@ -2378,10 +2384,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, COND_AL, args[0], args[1]);
break;
case INDEX_op_deposit_i32:
tcg_out_deposit(s, COND_AL, args[0], args[2],
args[3], args[4], const_args[2]);
@ -2438,7 +2440,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_bswap32_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
return C_O1_I1(r, r);

2
tcg/i386/tcg-target-has.h
View file

@ -26,7 +26,6 @@
#define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
/* optional instructions */
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@ -34,7 +33,6 @@
#if TCG_TARGET_REG_BITS == 64
/* Keep 32-bit values zero-extended in a register. */
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_add2_i64 1

23
tcg/i386/tcg-target.c.inc
View file

@ -3090,6 +3090,20 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, unsigned flags)
{
tcg_out_bswap32(s, a0);
if (flags & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, 0),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
@ -3193,13 +3207,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
OP_32_64(bswap32):
tcg_out_bswap32(s, a0);
if (rexw && (a2 & TCG_BSWAP_OS)) {
tcg_out_ext32s(s, a0, a0);
}
break;
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32);
break;
@ -3972,8 +3979,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64:
return C_O0_I2(re, r);
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_extrh_i64_i32:
return C_O1_I1(r, 0);

2
tcg/loongarch64/tcg-target-has.h
View file

@ -13,13 +13,11 @@
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
/* 64-bit operations */
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0

33
tcg/loongarch64/tcg-target.c.inc
View file

@ -1751,6 +1751,24 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, unsigned flags)
{
tcg_out_opc_revb_2w(s, a0, a1);
/* All 32-bit values are computed sign-extended in the register. */
if (type == TCG_TYPE_I32 || (flags & TCG_BSWAP_OS)) {
tcg_out_ext32s(s, a0, a0);
} else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext32u(s, a0, a0);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
@ -1842,19 +1860,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
break;
case INDEX_op_bswap32_i32:
/* All 32-bit values are computed sign-extended in the register. */
a2 = TCG_BSWAP_OS;
/* fallthrough */
case INDEX_op_bswap32_i64:
tcg_out_opc_revb_2w(s, a0, a1);
if (a2 & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
} else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext32u(s, a0, a0);
}
break;
case INDEX_op_bswap64_i64:
tcg_out_opc_revb_d(s, a0, a1);
break;
@ -2454,8 +2459,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:

2
tcg/mips/tcg-target-has.h
View file

@ -39,7 +39,6 @@ extern bool use_mips32r2_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_bswap32_i32 1
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_add2_i32 0
@ -56,7 +55,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#endif

54
tcg/mips/tcg-target.c.inc
View file

@ -710,26 +710,6 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
}
}
static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
if (flags & TCG_BSWAP_OZ) {
tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
}
} else {
if (flags & TCG_BSWAP_OZ) {
tcg_out_bswap_subr(s, bswap32u_addr);
} else {
tcg_out_bswap_subr(s, bswap32_addr);
}
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
@ -2170,6 +2150,32 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg, unsigned flags)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
if (flags & TCG_BSWAP_OZ) {
tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
}
} else {
if (flags & TCG_BSWAP_OZ) {
tcg_out_bswap_subr(s, bswap32u_addr);
} else {
tcg_out_bswap_subr(s, bswap32_addr);
}
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
@ -2261,12 +2267,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, i1, a0, a1, a2);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, a0, a1, 0);
break;
case INDEX_op_bswap32_i64:
tcg_out_bswap32(s, a0, a1, a2);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0, a1);
break;
@ -2371,7 +2371,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_bswap32_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
case INDEX_op_ld8u_i64:
@ -2381,7 +2380,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64:
case INDEX_op_ld32u_i64:
case INDEX_op_ld_i64:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:

2
tcg/ppc/tcg-target-has.h
View file

@ -17,7 +17,6 @@
#define have_vsx (cpuinfo & CPUINFO_VSX)
/* optional instructions */
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -25,7 +24,6 @@
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 1

84
tcg/ppc/tcg-target.c.inc
View file

@ -1012,41 +1012,6 @@ static void tcg_out_addpcis(TCGContext *s, TCGReg dst, intptr_t imm)
tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2);
}
static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags)
{
TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
if (have_isa_3_10) {
tcg_out32(s, BRW | RA(dst) | RS(src));
if (flags & TCG_BSWAP_OS) {
tcg_out_ext32s(s, dst, dst);
} else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext32u(s, dst, dst);
}
return;
}
/*
* Stolen from gcc's builtin_bswap32.
* In the following,
* dep(a, b, m) -> (a & ~m) | (b & m)
*
* Begin with: src = xxxxabcd
*/
/* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */
tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31);
/* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */
tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7);
/* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */
tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23);
if (flags & TCG_BSWAP_OS) {
tcg_out_ext32s(s, dst, tmp);
} else {
tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
}
}
static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
{
TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
@ -3384,6 +3349,47 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg dst, TCGReg src, unsigned flags)
{
TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
if (have_isa_3_10) {
tcg_out32(s, BRW | RA(dst) | RS(src));
if (flags & TCG_BSWAP_OS) {
tcg_out_ext32s(s, dst, dst);
} else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext32u(s, dst, dst);
}
return;
}
/*
* Stolen from gcc's builtin_bswap32.
* In the following,
* dep(a, b, m) -> (a & ~m) | (b & m)
*
* Begin with: src = xxxxabcd
*/
/* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */
tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31);
/* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */
tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7);
/* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */
tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23);
if (flags & TCG_BSWAP_OS) {
tcg_out_ext32s(s, dst, tmp);
} else {
tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out32(s, NEG | RT(a0) | RA(a1));
@ -3506,12 +3512,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, args[0], args[1], 0);
break;
case INDEX_op_bswap32_i64:
tcg_out_bswap32(s, args[0], args[1], args[2]);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, args[0], args[1]);
break;
@ -4252,7 +4252,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_bswap32_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
case INDEX_op_ld8u_i64:
@ -4264,7 +4263,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i64:

2
tcg/riscv/tcg-target-has.h
View file

@ -13,12 +13,10 @@
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1

30
tcg/riscv/tcg-target.c.inc
View file

@ -2424,6 +2424,23 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, unsigned flags)
{
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
if (flags & TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32);
} else {
tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_bswap,
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
@ -2509,17 +2526,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
case INDEX_op_bswap64_i64:
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
break;
case INDEX_op_bswap32_i32:
a2 = 0;
/* fall through */
case INDEX_op_bswap32_i64:
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
if (a2 & TCG_BSWAP_OZ) {
tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32);
} else {
tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32);
}
break;
case INDEX_op_add2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
@ -2858,8 +2864,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
return C_O1_I1(r, r);

2
tcg/s390x/tcg-target-has.h
View file

@ -29,14 +29,12 @@ extern uint64_t s390_facilities[3];
((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
/* optional instructions */
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 1

31
tcg/s390x/tcg-target.c.inc
View file

@ -2760,6 +2760,22 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, unsigned flags)
{
tcg_out_insn(s, RRE, LRVR, a0, a1);
if (flags & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
} else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext32u(s, a0, a0);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
if (type == TCG_TYPE_I32) {
@ -2846,19 +2862,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
break;
case INDEX_op_bswap32_i32:
tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
break;
case INDEX_op_bswap32_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
tcg_out_insn(s, RRE, LRVR, a0, a1);
if (a2 & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
} else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
tcg_out_ext32u(s, a0, a0);
}
break;
case INDEX_op_add2_i32:
if (const_args[4]) {
tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
@ -3459,8 +3462,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64:
return C_O0_I2(r, r);
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:

2
tcg/sparc64/tcg-target-has.h
View file

@ -14,14 +14,12 @@ extern bool use_vis3_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 1

4
tcg/sparc64/tcg-target.c.inc
View file

@ -1729,6 +1729,10 @@ static const TCGOutOpBswap outop_bswap16 = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_G0, a1);

1
tcg/tcg-has.h
View file

@ -12,7 +12,6 @@
#if TCG_TARGET_REG_BITS == 32
/* Turn some undef macros into false macros. */
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 0

4
tcg/tcg-op.c
View file

@ -1294,7 +1294,7 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags)
*/
void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
{
if (TCG_TARGET_HAS_bswap32_i32) {
if (tcg_op_supported(INDEX_op_bswap32_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3i_i32(INDEX_op_bswap32_i32, ret, arg, 0);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
@ -2137,7 +2137,7 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
} else {
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}
} else if (TCG_TARGET_HAS_bswap32_i64) {
} else if (tcg_op_supported(INDEX_op_bswap32_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg, flags);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();

8
tcg/tcg.c
View file

@ -1076,6 +1076,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_brcond, TCGOutOpBrcond, outop_brcond),
OUTOP(INDEX_op_bswap16, TCGOutOpBswap, outop_bswap16),
OUTOP(INDEX_op_bswap32_i32, TCGOutOpBswap, outop_bswap32),
OUTOP(INDEX_op_bswap32_i64, TCGOutOpBswap, outop_bswap32),
OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz),
OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop),
OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz),
@ -2342,8 +2344,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_add2_i32;
case INDEX_op_sub2_i32:
return TCG_TARGET_HAS_sub2_i32;
case INDEX_op_bswap32_i32:
return TCG_TARGET_HAS_bswap32_i32;
case INDEX_op_brcond2_i32:
case INDEX_op_setcond2_i32:
@ -2372,8 +2372,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
return TCG_TARGET_HAS_extr_i64_i32;
case INDEX_op_bswap32_i64:
return TCG_TARGET_HAS_bswap32_i64;
case INDEX_op_bswap64_i64:
return TCG_TARGET_HAS_bswap64_i64;
case INDEX_op_add2_i64:
@ -5488,6 +5486,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
break;
case INDEX_op_bswap16:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
{
const TCGOutOpBswap *out =
container_of(all_outop[op->opc], TCGOutOpBswap, base);

2
tcg/tci.c
View file

@ -690,12 +690,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap16(regs[r1]);
break;
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32)
tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap32(regs[r1]);
break;
#endif
#if TCG_TARGET_REG_BITS == 64
/* Load/store operations (64 bit). */

2
tcg/tci/tcg-target-has.h
View file

@ -7,13 +7,11 @@
#ifndef TCG_TARGET_HAS_H
#define TCG_TARGET_HAS_H
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i32 1

28
tcg/tci/tcg-target.c.inc
View file

@ -57,8 +57,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
@ -916,6 +914,20 @@ static const TCGOutOpBswap outop_bswap16 = {
.out_rr = tgen_bswap16,
};
static void tgen_bswap32(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, unsigned flags)
{
tcg_out_op_rr(s, INDEX_op_bswap32_i32, a0, a1);
if (flags & TCG_BSWAP_OS) {
tcg_out_sextract(s, TCG_TYPE_REG, a0, a0, 0, 32);
}
}
static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap32,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_op_rr(s, INDEX_op_neg, a0, a1);
@ -1026,8 +1038,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
int width;
switch (opc) {
case INDEX_op_goto_ptr:
tcg_out_op_r(s, opc, args[0]);
@ -1062,20 +1072,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_op_rrbb(s, opc, args[0], args[1], args[2], args[3]);
break;
case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
width = 32;
/* The base tci bswaps zero-extend, and ignore high bits. */
tcg_out_op_rr(s, opc, args[0], args[1]);
if (args[2] & TCG_BSWAP_OS) {
tcg_out_sextract(s, TCG_TYPE_REG, args[0], args[0], 0, width);
}
break;
CASE_32_64(add2)
CASE_32_64(sub2)
tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],