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tcg: Merge INDEX_op_neg_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
e126a91c38
commit
6971358747
7 changed files with 18 additions and 40 deletions
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@ -269,7 +269,7 @@ Arithmetic
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- | *t0* = *t1* - *t2*
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* - neg_i32/i64 *t0*, *t1*
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* - neg *t0*, *t1*
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- | *t0* = -*t1* (two's complement)
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@ -44,6 +44,7 @@ DEF(and, 1, 2, 0, TCG_OPF_INT)
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DEF(andc, 1, 2, 0, TCG_OPF_INT)
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DEF(eqv, 1, 2, 0, TCG_OPF_INT)
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DEF(nand, 1, 2, 0, TCG_OPF_INT)
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DEF(neg, 1, 1, 0, TCG_OPF_INT)
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DEF(nor, 1, 2, 0, TCG_OPF_INT)
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DEF(or, 1, 2, 0, TCG_OPF_INT)
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DEF(orc, 1, 2, 0, TCG_OPF_INT)
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@ -95,7 +96,6 @@ DEF(setcond2_i32, 1, 4, 1, 0)
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DEF(bswap16_i32, 1, 1, 1, 0)
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DEF(bswap32_i32, 1, 1, 1, 0)
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DEF(not_i32, 1, 1, 0, 0)
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DEF(neg_i32, 1, 1, 0, 0)
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DEF(clz_i32, 1, 2, 0, 0)
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DEF(ctz_i32, 1, 2, 0, 0)
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DEF(ctpop_i32, 1, 1, 0, 0)
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@ -145,7 +145,6 @@ DEF(bswap16_i64, 1, 1, 1, 0)
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DEF(bswap32_i64, 1, 1, 1, 0)
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DEF(bswap64_i64, 1, 1, 1, 0)
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DEF(not_i64, 1, 1, 0, 0)
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DEF(neg_i64, 1, 1, 0, 0)
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DEF(clz_i64, 1, 2, 0, 0)
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DEF(ctz_i64, 1, 2, 0, 0)
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DEF(ctpop_i64, 1, 1, 0, 0)
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@ -478,7 +478,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
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CASE_OP_32_64_VEC(not):
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return ~x;
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CASE_OP_32_64(neg):
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case INDEX_op_neg:
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return -x;
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case INDEX_op_andc:
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@ -2314,25 +2314,12 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
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break;
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}
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if (convert) {
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TCGOpcode neg_opc;
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if (!inv && !neg) {
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return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
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}
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switch (ctx->type) {
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case TCG_TYPE_I32:
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neg_opc = INDEX_op_neg_i32;
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break;
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case TCG_TYPE_I64:
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neg_opc = INDEX_op_neg_i64;
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break;
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default:
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g_assert_not_reached();
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}
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if (!inv) {
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op->opc = neg_opc;
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op->opc = INDEX_op_neg;
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} else if (neg) {
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op->opc = INDEX_op_add;
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op->args[2] = arg_new_constant(ctx, -1);
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@ -2348,7 +2335,7 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
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static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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{
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TCGOpcode neg_opc, shr_opc;
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TCGOpcode shr_opc;
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TCGOpcode uext_opc = 0, sext_opc = 0;
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TCGCond cond = op->args[3];
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TCGArg ret, src1, src2;
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@ -2371,7 +2358,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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switch (ctx->type) {
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case TCG_TYPE_I32:
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shr_opc = INDEX_op_shr_i32;
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neg_opc = INDEX_op_neg_i32;
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if (TCG_TARGET_extract_valid(TCG_TYPE_I32, sh, 1)) {
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uext_opc = INDEX_op_extract_i32;
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}
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@ -2381,7 +2367,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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break;
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case TCG_TYPE_I64:
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shr_opc = INDEX_op_shr_i64;
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neg_opc = INDEX_op_neg_i64;
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if (TCG_TARGET_extract_valid(TCG_TYPE_I64, sh, 1)) {
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uext_opc = INDEX_op_extract_i64;
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}
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@ -2432,7 +2417,7 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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op2->args[1] = ret;
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op2->args[2] = arg_new_constant(ctx, 1);
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} else if (neg) {
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op2 = opt_insert_after(ctx, op, neg_opc, 2);
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op2 = opt_insert_after(ctx, op, INDEX_op_neg, 2);
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op2->args[0] = ret;
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op2->args[1] = ret;
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}
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@ -2644,11 +2629,8 @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
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switch (ctx->type) {
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case TCG_TYPE_I32:
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neg_op = INDEX_op_neg_i32;
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have_neg = true;
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break;
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case TCG_TYPE_I64:
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neg_op = INDEX_op_neg_i64;
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neg_op = INDEX_op_neg;
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have_neg = true;
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break;
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case TCG_TYPE_V64:
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@ -2998,7 +2980,7 @@ void tcg_optimize(TCGContext *s)
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case INDEX_op_nand_vec:
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done = fold_nand(&ctx, op);
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break;
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CASE_OP_32_64(neg):
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case INDEX_op_neg:
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done = fold_neg(&ctx, op);
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break;
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case INDEX_op_nor:
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@ -396,7 +396,7 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
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tcg_gen_op2_i32(INDEX_op_neg, ret, arg);
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}
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void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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@ -1691,7 +1691,7 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
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void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
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{
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
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tcg_gen_op2_i64(INDEX_op_neg, ret, arg);
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} else {
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TCGv_i32 zero = tcg_constant_i32(0);
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tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
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@ -1022,8 +1022,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
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OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
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OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
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OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
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OUTOP(INDEX_op_neg_i32, TCGOutOpUnary, outop_neg),
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OUTOP(INDEX_op_neg_i64, TCGOutOpUnary, outop_neg),
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OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
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OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
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OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
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OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
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@ -5476,8 +5475,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
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}
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break;
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case INDEX_op_neg_i32:
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case INDEX_op_neg_i64:
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case INDEX_op_neg:
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{
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const TCGOutOpUnary *out =
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container_of(all_outop[op->opc], TCGOutOpUnary, base);
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11
tcg/tci.c
11
tcg/tci.c
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@ -567,6 +567,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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tci_args_rrr(insn, &r0, &r1, &r2);
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regs[r0] = ~(regs[r1] | regs[r2]);
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break;
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case INDEX_op_neg:
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = -regs[r1];
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break;
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/* Arithmetic operations (32 bit). */
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@ -697,10 +701,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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regs[r0] = ~regs[r1];
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break;
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#endif
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CASE_32_64(neg)
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = -regs[r1];
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break;
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#if TCG_TARGET_REG_BITS == 64
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/* Load/store operations (64 bit). */
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@ -1054,6 +1054,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
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break;
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case INDEX_op_mov:
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case INDEX_op_neg:
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case INDEX_op_ext_i32_i64:
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case INDEX_op_extu_i32_i64:
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case INDEX_op_bswap16_i32:
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@ -1063,8 +1064,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
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case INDEX_op_bswap64_i64:
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case INDEX_op_not_i32:
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case INDEX_op_not_i64:
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case INDEX_op_neg_i32:
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case INDEX_op_neg_i64:
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case INDEX_op_ctpop_i32:
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case INDEX_op_ctpop_i64:
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tci_args_rr(insn, &r0, &r1);
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@ -731,7 +731,7 @@ static const TCGOutOpBinary outop_xor = {
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static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
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{
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tcg_out_op_rr(s, glue(INDEX_op_neg_i,TCG_TARGET_REG_BITS), a0, a1);
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tcg_out_op_rr(s, INDEX_op_neg, a0, a1);
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}
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static const TCGOutOpUnary outop_neg = {
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