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tcg: Convert neg to TCGOutOpUnary

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 22:37:07 -08:00
parent 60f34f55f1
commit e126a91c38
11 changed files with 125 additions and 67 deletions
Download patch file Download diff file Expand all files Collapse all files

18
tcg/aarch64/tcg-target.c.inc
View file

@ -2235,6 +2235,17 @@ static const TCGOutOpBinary outop_xor = {
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_XZR, a1);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
@ -2301,11 +2312,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
break;
case INDEX_op_neg_i64:
case INDEX_op_neg_i32:
tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
break;
case INDEX_op_not_i64:
case INDEX_op_not_i32:
tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1);
@ -2990,8 +2996,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_bswap16_i32:

14
tcg/arm/tcg-target.c.inc
View file

@ -1951,6 +1951,16 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_subfi(s, type, a0, 0, a1);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2040,9 +2050,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
tcg_out_mov_reg(s, COND_AL, args[0], a0);
break;
case INDEX_op_neg_i32:
tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
break;
case INDEX_op_not_i32:
tcg_out_dat_reg(s, COND_AL,
ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
@ -2226,7 +2233,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32:

16
tcg/i386/tcg-target.c.inc
View file

@ -2701,6 +2701,17 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, 0),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2900,9 +2911,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
OP_32_64(neg):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0);
break;
OP_32_64(not):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
break;
@ -3719,8 +3727,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_extrh_i64_i32:

19
tcg/loongarch64/tcg-target.c.inc
View file

@ -1409,6 +1409,16 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1611,13 +1621,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_neg_i32:
tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_neg_i64:
tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_mul_i32:
tcg_out_opc_mul_w(s, a0, a1, a2);
break;
@ -2272,8 +2275,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_extract_i32:

18
tcg/mips/tcg-target.c.inc
View file

@ -1783,6 +1783,16 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1975,12 +1985,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
break;
case INDEX_op_neg_i32:
i1 = OPC_SUBU;
goto do_unary;
case INDEX_op_neg_i64:
i1 = OPC_DSUBU;
goto do_unary;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
i1 = OPC_NOR;
@ -2195,7 +2199,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32:
@ -2208,7 +2211,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64:
case INDEX_op_ld32u_i64:
case INDEX_op_ld_i64:
case INDEX_op_neg_i64:
case INDEX_op_not_i64:
case INDEX_op_bswap16_i64:
case INDEX_op_bswap32_i64:

17
tcg/ppc/tcg-target.c.inc
View file

@ -3052,6 +3052,16 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out32(s, NEG | RT(a0) | RA(a1));
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -3224,11 +3234,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_brcond2(s, args, const_args);
break;
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
@ -4119,7 +4124,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_ctpop_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32:
@ -4133,7 +4137,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
case INDEX_op_ctpop_i64:
case INDEX_op_neg_i64:
case INDEX_op_not_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:

19
tcg/riscv/tcg-target.c.inc
View file

@ -2077,6 +2077,16 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2145,13 +2155,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
break;
case INDEX_op_neg_i32:
tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_neg_i64:
tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_mul_i32:
tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
break;
@ -2660,7 +2663,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_not_i32:
case INDEX_op_neg_i32:
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i64:
@ -2669,7 +2671,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64:
case INDEX_op_ld_i64:
case INDEX_op_not_i64:
case INDEX_op_neg_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:

22
tcg/s390x/tcg-target.c.inc
View file

@ -2373,6 +2373,20 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori_3,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RR, LCR, a0, a1);
} else {
tcg_out_insn(s, RRE, LCGR, a0, a1);
}
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
# define OP_32_64(x) \
case glue(glue(INDEX_op_,x),_i32): \
@ -2430,9 +2444,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
break;
case INDEX_op_neg_i32:
tcg_out_insn(s, RR, LCR, args[0], args[1]);
break;
case INDEX_op_not_i32:
tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]);
break;
@ -2624,9 +2635,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
break;
case INDEX_op_neg_i64:
tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
break;
case INDEX_op_not_i64:
tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]);
break;
@ -3323,8 +3331,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_ext_i32_i64:

15
tcg/sparc64/tcg-target.c.inc
View file

@ -1403,6 +1403,16 @@ static const TCGOutOpBinary outop_xor = {
.out_rri = tgen_xori,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_G0, a1);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1473,9 +1483,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
c = ARITH_UMUL;
goto gen_arith;
OP_32_64(neg):
c = ARITH_SUB;
goto gen_arith1;
OP_32_64(not):
c = ARITH_ORN;
goto gen_arith1;
@ -1639,8 +1646,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_ext_i32_i64:

21
tcg/tcg.c
View file

@ -986,6 +986,11 @@ typedef struct TCGOutOpBinary {
TCGReg a0, TCGReg a1, tcg_target_long a2);
} TCGOutOpBinary;
typedef struct TCGOutOpUnary {
TCGOutOp base;
void (*out_rr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1);
} TCGOutOpUnary;
typedef struct TCGOutOpSubtract {
TCGOutOp base;
void (*out_rrr)(TCGContext *s, TCGType type,
@ -1017,6 +1022,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_neg_i32, TCGOutOpUnary, outop_neg),
OUTOP(INDEX_op_neg_i64, TCGOutOpUnary, outop_neg),
OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
@ -2240,7 +2247,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
case INDEX_op_st_i32:
case INDEX_op_neg_i32:
case INDEX_op_mul_i32:
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@ -2309,7 +2315,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
case INDEX_op_neg_i64:
case INDEX_op_mul_i64:
case INDEX_op_shl_i64:
case INDEX_op_shr_i64:
@ -5471,6 +5476,18 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
break;
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
{
const TCGOutOpUnary *out =
container_of(all_outop[op->opc], TCGOutOpUnary, base);
/* Constants should have been folded. */
tcg_debug_assert(!const_args[1]);
out->out_rr(s, type, new_args[0], new_args[1]);
}
break;
default:
if (def->flags & TCG_OPF_VECTOR) {
tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64,

13
tcg/tci/tcg-target.c.inc
View file

@ -57,8 +57,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_bswap16_i32:
@ -731,6 +729,16 @@ static const TCGOutOpBinary outop_xor = {
.out_rrr = tgen_xor,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_op_rr(s, glue(INDEX_op_neg_i,TCG_TARGET_REG_BITS), a0, a1);
}
static const TCGOutOpUnary outop_neg = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_neg,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -804,7 +812,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3]));
break;
CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */
case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */