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hw/intc/aspeed: Rename num_ints to num_inpins for clarity

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To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-12-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:20 +08:00 • committed by Cédric Le Goater
parent 28194d5d15
commit 63f3618f9b
3 changed files with 24 additions and 20 deletions
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11
include/hw/intc/aspeed_intc.h
View file

@ -17,6 +17,7 @@
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_INTS 9
#define ASPEED_INTC_MAX_INPINS 9
struct AspeedINTCState {
/*< private >*/
@ -27,19 +28,19 @@ struct AspeedINTCState {
MemoryRegion iomem_container;
uint32_t *regs;
OrIRQState orgates[ASPEED_INTC_NR_INTS];
OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
qemu_irq output_pins[ASPEED_INTC_NR_INTS];
uint32_t enable[ASPEED_INTC_NR_INTS];
uint32_t mask[ASPEED_INTC_NR_INTS];
uint32_t pending[ASPEED_INTC_NR_INTS];
uint32_t enable[ASPEED_INTC_MAX_INPINS];
uint32_t mask[ASPEED_INTC_MAX_INPINS];
uint32_t pending[ASPEED_INTC_MAX_INPINS];
};
struct AspeedINTCClass {
SysBusDeviceClass parent_class;
uint32_t num_lines;
uint32_t num_ints;
uint32_t num_inpins;
uint64_t mem_size;
uint64_t nr_regs;
uint64_t reg_offset;