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To support AST2700 A1, some registers of the INTC(CPU Die) support one input pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC controller code for better clarity and consistency in naming conventions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
50 lines
1.1 KiB
C
50 lines
1.1 KiB
C
/*
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* ASPEED INTC Controller
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*
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* Copyright (C) 2024 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_INTC_H
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#define ASPEED_INTC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "hw/or-irq.h"
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#define TYPE_ASPEED_INTC "aspeed.intc"
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#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
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OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
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#define ASPEED_INTC_NR_INTS 9
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#define ASPEED_INTC_MAX_INPINS 9
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struct AspeedINTCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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MemoryRegion iomem_container;
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uint32_t *regs;
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OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
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qemu_irq output_pins[ASPEED_INTC_NR_INTS];
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uint32_t enable[ASPEED_INTC_MAX_INPINS];
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uint32_t mask[ASPEED_INTC_MAX_INPINS];
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uint32_t pending[ASPEED_INTC_MAX_INPINS];
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};
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struct AspeedINTCClass {
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SysBusDeviceClass parent_class;
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uint32_t num_lines;
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uint32_t num_inpins;
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uint64_t mem_size;
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uint64_t nr_regs;
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uint64_t reg_offset;
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const MemoryRegionOps *reg_ops;
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};
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#endif /* ASPEED_INTC_H */
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