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tcg: Convert bswap64 to TCGOutOpUnary

Browse source 
Use TCGOutOpUnary instead of TCGOutOpBswap because the
flags are not used with this opcode; they are merely
present for uniformity with the smaller bswaps.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-10 21:46:38 -08:00
parent 7498d882cb
commit 613b571c93
23 changed files with 144 additions and 104 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tcg/aarch64/tcg-target-has.h
View file

@ -19,7 +19,6 @@
#define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1

15
tcg/aarch64/tcg-target.c.inc
View file

@ -2470,6 +2470,16 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tgen_sub(s, type, a0, TCG_REG_XZR, a1); tgen_sub(s, type, a0, TCG_REG_XZR, a1);
@ -2637,10 +2647,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false); tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false);
break; break;
case INDEX_op_bswap64_i64:
tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
break;
case INDEX_op_deposit_i64: case INDEX_op_deposit_i64:
case INDEX_op_deposit_i32: case INDEX_op_deposit_i32:
tcg_out_dep(s, ext, a0, a2, args[3], args[4]); tcg_out_dep(s, ext, a0, a2, args[3], args[4]);
@ -3159,7 +3165,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:

4
tcg/arm/tcg-target.c.inc
View file

@ -2163,6 +2163,10 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tgen_subfi(s, type, a0, 0, a1); tgen_subfi(s, type, a0, 0, a1);

1
tcg/i386/tcg-target-has.h
View file

@ -33,7 +33,6 @@
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
/* Keep 32-bit values zero-extended in a register. */ /* Keep 32-bit values zero-extended in a register. */
#define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1

16
tcg/i386/tcg-target.c.inc
View file

@ -3104,6 +3104,18 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
#if TCG_TARGET_REG_BITS == 64
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_bswap64(s, a0);
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, 0),
.out_rr = tgen_bswap64,
};
#endif
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
@ -3279,9 +3291,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0);
break;
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:
tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32);
break; break;
@ -3979,7 +3988,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64: case INDEX_op_st_i64:
return C_O0_I2(re, r); return C_O0_I2(re, r);
case INDEX_op_bswap64_i64:
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:
return C_O1_I1(r, 0); return C_O1_I1(r, 0);

1
tcg/loongarch64/tcg-target-has.h
View file

@ -18,7 +18,6 @@
/* 64-bit operations */ /* 64-bit operations */
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0

15
tcg/loongarch64/tcg-target.c.inc
View file

@ -1769,6 +1769,16 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_opc_revb_d(s, a0, a1);
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tgen_sub(s, type, a0, TCG_REG_ZERO, a1); tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
@ -1860,10 +1870,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
break; break;
case INDEX_op_bswap64_i64:
tcg_out_opc_revb_d(s, a0, a1);
break;
case INDEX_op_ld8s_i32: case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64: case INDEX_op_ld8s_i64:
tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
@ -2459,7 +2465,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extract_i64: case INDEX_op_extract_i64:
case INDEX_op_sextract_i32: case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64: case INDEX_op_sextract_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ld8s_i32: case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64: case INDEX_op_ld8s_i64:
case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i32:

1
tcg/mips/tcg-target-has.h
View file

@ -55,7 +55,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#endif #endif

37
tcg/mips/tcg-target.c.inc
View file

@ -710,19 +710,6 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
} }
} }
static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
} else {
tcg_out_bswap_subr(s, bswap64_addr);
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
{ {
tcg_debug_assert(TCG_TARGET_REG_BITS == 64); tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
@ -2176,6 +2163,26 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
#if TCG_TARGET_REG_BITS == 64
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
} else {
tcg_out_bswap_subr(s, bswap64_addr);
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
#endif /* TCG_TARGET_REG_BITS == 64 */
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tgen_sub(s, type, a0, TCG_REG_ZERO, a1); tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
@ -2267,9 +2274,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, i1, a0, a1, a2); tcg_out_ldst(s, i1, a0, a1, a2);
break; break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0, a1);
break;
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:
tcg_out_dsra(s, a0, a1, 32); tcg_out_dsra(s, a0, a1, 32);
break; break;
@ -2380,7 +2384,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32: case INDEX_op_extrl_i64_i32:

1
tcg/ppc/tcg-target-has.h
View file

@ -24,7 +24,6 @@
#define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1

88
tcg/ppc/tcg-target.c.inc
View file

@ -1012,44 +1012,6 @@ static void tcg_out_addpcis(TCGContext *s, TCGReg dst, intptr_t imm)
tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2); tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2);
} }
static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
{
TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
TCGReg t1 = dst == src ? dst : TCG_REG_R0;
if (have_isa_3_10) {
tcg_out32(s, BRD | RA(dst) | RS(src));
return;
}
/*
* In the following,
* dep(a, b, m) -> (a & ~m) | (b & m)
*
* Begin with: src = abcdefgh
*/
/* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */
tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31);
/* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */
tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7);
/* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */
tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23);
/* t0 = rol64(t0, 32) = hgfe0000 */
tcg_out_rld(s, RLDICL, t0, t0, 32, 0);
/* t1 = rol64(src, 32) = efghabcd */
tcg_out_rld(s, RLDICL, t1, src, 32, 0);
/* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */
tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31);
/* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */
tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7);
/* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */
tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23);
tcg_out_mov(s, TCG_TYPE_REG, dst, t0);
}
/* Emit a move into ret of arg, if it can be done in one insn. */ /* Emit a move into ret of arg, if it can be done in one insn. */
static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
{ {
@ -3390,6 +3352,51 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
#if TCG_TARGET_REG_BITS == 64
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
{
TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
TCGReg t1 = dst == src ? dst : TCG_REG_R0;
if (have_isa_3_10) {
tcg_out32(s, BRD | RA(dst) | RS(src));
return;
}
/*
* In the following,
* dep(a, b, m) -> (a & ~m) | (b & m)
*
* Begin with: src = abcdefgh
*/
/* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */
tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31);
/* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */
tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7);
/* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */
tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23);
/* t0 = rol64(t0, 32) = hgfe0000 */
tcg_out_rld(s, RLDICL, t0, t0, 32, 0);
/* t1 = rol64(src, 32) = efghabcd */
tcg_out_rld(s, RLDICL, t1, src, 32, 0);
/* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */
tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31);
/* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */
tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7);
/* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */
tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23);
tcg_out_mov(s, TCG_TYPE_REG, dst, t0);
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
#endif /* TCG_TARGET_REG_BITS == 64 */
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tcg_out32(s, NEG | RT(a0) | RA(a1)); tcg_out32(s, NEG | RT(a0) | RA(a1));
@ -3512,10 +3519,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
break; break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, args[0], args[1]);
break;
case INDEX_op_deposit_i32: case INDEX_op_deposit_i32:
if (const_args[2]) { if (const_args[2]) {
uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
@ -4263,7 +4266,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_extract_i64: case INDEX_op_extract_i64:
case INDEX_op_sextract_i64: case INDEX_op_sextract_i64:
return C_O1_I1(r, r); return C_O1_I1(r, r);

1
tcg/riscv/tcg-target-has.h
View file

@ -17,7 +17,6 @@
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1

16
tcg/riscv/tcg-target.c.inc
View file

@ -2441,6 +2441,17 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_bswap,
.out_rr = tgen_bswap64,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tgen_sub(s, type, a0, TCG_REG_ZERO, a1); tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
@ -2523,10 +2534,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, OPC_SD, a0, a1, a2); tcg_out_ldst(s, OPC_SD, a0, a1, a2);
break; break;
case INDEX_op_bswap64_i64:
tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
break;
case INDEX_op_add2_i32: case INDEX_op_add2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], false, true); const_args[4], const_args[5], false, true);
@ -2864,7 +2871,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extract_i64: case INDEX_op_extract_i64:
case INDEX_op_sextract_i32: case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64: case INDEX_op_sextract_i64:
case INDEX_op_bswap64_i64:
return C_O1_I1(r, r); return C_O1_I1(r, r);
case INDEX_op_st8_i32: case INDEX_op_st8_i32:

1
tcg/s390x/tcg-target-has.h
View file

@ -35,7 +35,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1

15
tcg/s390x/tcg-target.c.inc
View file

@ -2776,6 +2776,16 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_insn(s, RRE, LRVGR, a0, a1);
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
if (type == TCG_TYPE_I32) { if (type == TCG_TYPE_I32) {
@ -2922,10 +2932,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
break; break;
case INDEX_op_bswap64_i64:
tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
break;
case INDEX_op_add2_i64: case INDEX_op_add2_i64:
if (const_args[4]) { if (const_args[4]) {
if ((int64_t)args[4] >= 0) { if ((int64_t)args[4] >= 0) {
@ -3462,7 +3468,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64: case INDEX_op_st_i64:
return C_O0_I2(r, r); return C_O0_I2(r, r);
case INDEX_op_bswap64_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:

1
tcg/sparc64/tcg-target-has.h
View file

@ -20,7 +20,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1

4
tcg/sparc64/tcg-target.c.inc
View file

@ -1733,6 +1733,10 @@ static const TCGOutOpBswap outop_bswap32 = {
.base.static_constraint = C_NotImplemented, .base.static_constraint = C_NotImplemented,
}; };
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tgen_sub(s, type, a0, TCG_REG_G0, a1); tgen_sub(s, type, a0, TCG_REG_G0, a1);

1
tcg/tcg-has.h
View file

@ -12,7 +12,6 @@
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
/* Turn some undef macros into false macros. */ /* Turn some undef macros into false macros. */
#define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0

2
tcg/tcg-op.c
View file

@ -2184,7 +2184,7 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
} else if (TCG_TARGET_HAS_bswap64_i64) { } else if (tcg_op_supported(INDEX_op_bswap64_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0); tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0);
} else { } else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64(); TCGv_i64 t0 = tcg_temp_ebb_new_i64();

7
tcg/tcg.c
View file

@ -1112,6 +1112,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2), OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2),
OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2),
#else
OUTOP(INDEX_op_bswap64_i64, TCGOutOpUnary, outop_bswap64),
#endif #endif
}; };
@ -2371,8 +2373,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extrl_i64_i32: case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:
return TCG_TARGET_HAS_extr_i64_i32; return TCG_TARGET_HAS_extr_i64_i32;
case INDEX_op_bswap64_i64:
return TCG_TARGET_HAS_bswap64_i64;
case INDEX_op_add2_i64: case INDEX_op_add2_i64:
return TCG_TARGET_HAS_add2_i64; return TCG_TARGET_HAS_add2_i64;
case INDEX_op_sub2_i64: case INDEX_op_sub2_i64:
@ -5470,6 +5470,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
} }
break; break;
case INDEX_op_bswap64_i64:
assert(TCG_TARGET_REG_BITS == 64);
/* fall through */
case INDEX_op_ctpop: case INDEX_op_ctpop:
case INDEX_op_neg: case INDEX_op_neg:
case INDEX_op_not: case INDEX_op_not:

2
tcg/tci.c
View file

@ -788,12 +788,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rr(insn, &r0, &r1); tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint32_t)regs[r1]; regs[r0] = (uint32_t)regs[r1];
break; break;
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:
tci_args_rr(insn, &r0, &r1); tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap64(regs[r1]); regs[r0] = bswap64(regs[r1]);
break; break;
#endif
#endif /* TCG_TARGET_REG_BITS == 64 */ #endif /* TCG_TARGET_REG_BITS == 64 */
/* QEMU specific operations. */ /* QEMU specific operations. */

1
tcg/tci/tcg-target-has.h
View file

@ -12,7 +12,6 @@
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1

17
tcg/tci/tcg-target.c.inc
View file

@ -57,7 +57,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:
case INDEX_op_extract_i64: case INDEX_op_extract_i64:
case INDEX_op_sextract_i32: case INDEX_op_sextract_i32:
@ -928,6 +927,18 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32, .out_rr = tgen_bswap32,
}; };
#if TCG_TARGET_REG_BITS == 64
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_op_rr(s, INDEX_op_bswap64_i64, a0, a1);
}
static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
#endif
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tcg_out_op_rr(s, INDEX_op_neg, a0, a1); tcg_out_op_rr(s, INDEX_op_neg, a0, a1);
@ -1072,10 +1083,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_op_rrbb(s, opc, args[0], args[1], args[2], args[3]); tcg_out_op_rrbb(s, opc, args[0], args[1], args[2], args[3]);
break; break;
case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
CASE_32_64(add2) CASE_32_64(add2)
CASE_32_64(sub2) CASE_32_64(sub2)
tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],