motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 15:53:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg: Convert extract to TCGOutOpExtract

Browse source 
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-11 07:55:47 -08:00
parent 3ad5d4ccb4
commit 5a4d034f3c
11 changed files with 191 additions and 152 deletions
Download patch file Download diff file Expand all files Collapse all files

28
tcg/aarch64/tcg-target.c.inc
View file

@ -2567,6 +2567,22 @@ static const TCGOutOpMovcond outop_movcond = {
.out = tgen_movcond,
};
static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len)
{
if (ofs == 0) {
uint64_t mask = MAKE_64BIT_MASK(0, len);
tcg_out_logicali(s, I3404_ANDI, type, a0, a1, mask);
} else {
tcg_out_ubfm(s, type, a0, a1, ofs, ofs + len - 1);
}
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
@ -2652,16 +2668,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_dep(s, ext, a0, a2, args[3], args[4]);
break;
case INDEX_op_extract_i64:
case INDEX_op_extract_i32:
if (a2 == 0) {
uint64_t mask = MAKE_64BIT_MASK(0, args[3]);
tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, mask);
} else {
tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
}
break;
case INDEX_op_sextract_i64:
case INDEX_op_sextract_i32:
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
@ -3167,8 +3173,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
return C_O1_I1(r, r);

23
tcg/arm/tcg-target.c.inc
View file

@ -981,19 +981,19 @@ static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd,
| (ofs << 7) | ((ofs + len - 1) << 16));
}
static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd,
TCGReg rn, int ofs, int len)
static void tgen_extract(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn,
unsigned ofs, unsigned len)
{
/* According to gcc, AND can be faster. */
if (ofs == 0 && len <= 8) {
tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn,
tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn,
encode_imm_nofail((1 << len) - 1));
return;
}
if (use_armv7_instructions) {
/* ubfx */
tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn
tcg_out32(s, 0x07e00050 | (COND_AL << 28) | (rd << 12) | rn
| (ofs << 7) | ((len - 1) << 16));
return;
}
@ -1002,17 +1002,24 @@ static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd,
switch (len) {
case 8:
/* uxtb */
tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
tcg_out32(s, 0x06ef0070 | (COND_AL << 28) |
(rd << 12) | (ofs << 7) | rn);
break;
case 16:
/* uxth */
tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
tcg_out32(s, 0x06ff0070 | (COND_AL << 28) |
(rd << 12) | (ofs << 7) | rn);
break;
default:
g_assert_not_reached();
}
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd,
TCGReg rn, int ofs, int len)
{
@ -2392,9 +2399,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_deposit(s, COND_AL, args[0], args[2],
args[3], args[4], const_args[2]);
break;
case INDEX_op_extract_i32:
tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]);
break;
case INDEX_op_sextract_i32:
tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
break;
@ -2444,7 +2448,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
return C_O1_I1(r, r);

77
tcg/i386/tcg-target.c.inc
View file

@ -3138,6 +3138,47 @@ static const TCGOutOpUnary outop_not = {
.out_rr = tgen_not,
};
static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len)
{
if (ofs == 0) {
switch (len) {
case 8:
tcg_out_ext8u(s, a0, a1);
return;
case 16:
tcg_out_ext16u(s, a0, a1);
return;
case 32:
tcg_out_ext32u(s, a0, a1);
return;
}
} else if (TCG_TARGET_REG_BITS == 64 && ofs + len == 32) {
/* This is a 32-bit zero-extending right shift. */
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
tcg_out_shifti(s, SHIFT_SHR, a0, ofs);
return;
} else if (ofs == 8 && len == 8) {
/*
* On the off-chance that we can use the high-byte registers.
* Otherwise we emit the same ext16 + shift pattern that we
* would have gotten from the normal tcg-op.c expansion.
*/
if (a1 < 4 && (TCG_TARGET_REG_BITS == 32 || a0 < 8)) {
tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4);
} else {
tcg_out_ext16u(s, a0, a1);
tcg_out_shifti(s, SHIFT_SHR, a0, 8);
}
return;
}
g_assert_not_reached();
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -3328,40 +3369,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_extract_i64:
if (a2 + args[3] == 32) {
if (a2 == 0) {
tcg_out_ext32u(s, a0, a1);
break;
}
/* This is a 32-bit zero-extending right shift. */
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
tcg_out_shifti(s, SHIFT_SHR, a0, a2);
break;
}
/* FALLTHRU */
case INDEX_op_extract_i32:
if (a2 == 0 && args[3] == 8) {
tcg_out_ext8u(s, a0, a1);
} else if (a2 == 0 && args[3] == 16) {
tcg_out_ext16u(s, a0, a1);
} else if (a2 == 8 && args[3] == 8) {
/*
* On the off-chance that we can use the high-byte registers.
* Otherwise we emit the same ext16 + shift pattern that we
* would have gotten from the normal tcg-op.c expansion.
*/
if (a1 < 4 && a0 < 8) {
tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4);
} else {
tcg_out_ext16u(s, a0, a1);
tcg_out_shifti(s, SHIFT_SHR, a0, 8);
}
} else {
g_assert_not_reached();
}
break;
case INDEX_op_sextract_i64:
if (a2 == 0 && args[3] == 8) {
tcg_out_ext8s(s, TCG_TYPE_I64, a0, a1);
@ -3994,8 +4001,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
return C_O1_I1(r, r);

33
tcg/loongarch64/tcg-target.c.inc
View file

@ -1799,6 +1799,22 @@ static const TCGOutOpUnary outop_not = {
.out_rr = tgen_not,
};
static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len)
{
if (ofs == 0 && len <= 12) {
tcg_out_opc_andi(s, a0, a1, (1 << len) - 1);
} else if (type == TCG_TYPE_I32) {
tcg_out_opc_bstrpick_w(s, a0, a1, ofs, ofs + len - 1);
} else {
tcg_out_opc_bstrpick_d(s, a0, a1, ofs, ofs + len - 1);
}
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1828,21 +1844,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_srai_d(s, a0, a1, 32);
break;
case INDEX_op_extract_i32:
if (a2 == 0 && args[3] <= 12) {
tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1);
} else {
tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
}
break;
case INDEX_op_extract_i64:
if (a2 == 0 && args[3] <= 12) {
tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1);
} else {
tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
}
break;
case INDEX_op_sextract_i64:
if (a2 + args[3] == 32) {
if (a2 == 0) {
@ -2461,8 +2462,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
case INDEX_op_ld8s_i32:

35
tcg/mips/tcg-target.c.inc
View file

@ -2203,6 +2203,23 @@ static const TCGOutOpUnary outop_not = {
.out_rr = tgen_not,
};
static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len)
{
if (ofs == 0 && len <= 16) {
tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << len) - 1);
} else if (type == TCG_TYPE_I32) {
tcg_out_opc_bf(s, OPC_EXT, a0, a1, len - 1, ofs);
} else {
tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU,
a0, a1, len - 1, ofs);
}
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2286,22 +2303,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
args[3] + args[4] - 1, args[3]);
break;
case INDEX_op_extract_i32:
if (a2 == 0 && args[3] <= 16) {
tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
} else {
tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
}
break;
case INDEX_op_extract_i64:
if (a2 == 0 && args[3] <= 16) {
tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
} else {
tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU,
a0, a1, args[3] - 1, a2);
}
break;
case INDEX_op_sextract_i64:
if (a2 == 0 && args[3] == 32) {
tcg_out_ext32s(s, a0, a1);
@ -2375,7 +2376,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64:
@ -2388,7 +2388,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i64:
return C_O1_I1(r, r);

35
tcg/ppc/tcg-target.c.inc
View file

@ -3417,6 +3417,23 @@ static const TCGOutOpUnary outop_not = {
.out_rr = tgen_not,
};
static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len)
{
if (ofs == 0 && len <= 16) {
tgen_andi(s, TCG_TYPE_I32, a0, a1, (1 << len) - 1);
} else if (type == TCG_TYPE_I32) {
tcg_out_rlw(s, RLWINM, a0, a1, 32 - ofs, 32 - len, 31);
} else {
tcg_out_rld(s, RLDICL, a0, a1, 64 - ofs, 64 - len);
}
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -3538,22 +3555,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_extract_i32:
if (args[2] == 0 && args[3] <= 16) {
tcg_out32(s, ANDI | SAI(args[1], args[0], (1 << args[3]) - 1));
break;
}
tcg_out_rlw(s, RLWINM, args[0], args[1],
32 - args[2], 32 - args[3], 31);
break;
case INDEX_op_extract_i64:
if (args[2] == 0 && args[3] <= 16) {
tcg_out32(s, ANDI | SAI(args[1], args[0], (1 << args[3]) - 1));
break;
}
tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
break;
case INDEX_op_sextract_i64:
if (args[2] + args[3] == 32) {
if (args[2] == 0) {
@ -4255,7 +4256,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64:
@ -4266,7 +4266,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i64:
return C_O1_I1(r, r);

54
tcg/riscv/tcg-target.c.inc
View file

@ -2472,6 +2472,34 @@ static const TCGOutOpUnary outop_not = {
.out_rr = tgen_not,
};
static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len)
{
if (ofs == 0) {
switch (len) {
case 16:
tcg_out_ext16u(s, a0, a1);
return;
case 32:
tcg_out_ext32u(s, a0, a1);
return;
}
}
if (ofs + len == 32) {
tgen_shli(s, TCG_TYPE_I32, a0, a1, ofs);
return;
}
if (len == 1) {
tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, ofs);
return;
}
g_assert_not_reached();
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2572,30 +2600,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_mb(s, a0);
break;
case INDEX_op_extract_i64:
if (a2 + args[3] == 32) {
if (a2 == 0) {
tcg_out_ext32u(s, a0, a1);
} else {
tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
}
break;
}
/* FALLTHRU */
case INDEX_op_extract_i32:
switch (args[3]) {
case 1:
tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2);
break;
case 16:
tcg_debug_assert(a2 == 0);
tcg_out_ext16u(s, a0, a1);
break;
default:
g_assert_not_reached();
}
break;
case INDEX_op_sextract_i64:
if (a2 + args[3] == 32) {
if (a2 == 0) {
@ -2867,8 +2871,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
return C_O1_I1(r, r);

14
tcg/s390x/tcg-target.c.inc
View file

@ -1563,8 +1563,8 @@ static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
}
static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
int ofs, int len)
static void tgen_extract(TCGContext *s, TCGType type, TCGReg dest,
TCGReg src, unsigned ofs, unsigned len)
{
if (ofs == 0) {
switch (len) {
@ -1582,6 +1582,11 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tgen_sextract(TCGContext *s, TCGReg dest, TCGReg src,
int ofs, int len)
{
@ -2975,9 +2980,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
OP_32_64(extract):
tgen_extract(s, args[0], args[1], args[2], args[3]);
break;
OP_32_64(sextract):
tgen_sextract(s, args[0], args[1], args[2], args[3]);
break;
@ -3470,8 +3472,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
return C_O1_I1(r, r);

16
tcg/sparc64/tcg-target.c.inc
View file

@ -1757,6 +1757,17 @@ static const TCGOutOpUnary outop_not = {
.out_rr = tgen_not,
};
static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len)
{
tcg_debug_assert(ofs + len == 32);
tcg_out_arithi(s, a0, a1, ofs, SHIFT_SRL);
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extract,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1857,10 +1868,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_mb(s, a0);
break;
case INDEX_op_extract_i64:
tcg_debug_assert(a2 + args[3] == 32);
tcg_out_arithi(s, a0, a1, a2, SHIFT_SRL);
break;
case INDEX_op_sextract_i64:
tcg_debug_assert(a2 + args[3] == 32);
tcg_out_arithi(s, a0, a1, a2, SHIFT_SRA);
@ -1897,7 +1904,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i64:
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:

20
tcg/tcg.c
View file

@ -1013,6 +1013,12 @@ typedef struct TCGOutOpDivRem {
TCGReg a0, TCGReg a1, TCGReg a4);
} TCGOutOpDivRem;
typedef struct TCGOutOpExtract {
TCGOutOp base;
void (*out_rr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
unsigned ofs, unsigned len);
} TCGOutOpExtract;
typedef struct TCGOutOpMovcond {
TCGOutOp base;
void (*out)(TCGContext *s, TCGType type, TCGCond cond,
@ -1085,6 +1091,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2),
OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_extract_i32, TCGOutOpExtract, outop_extract),
OUTOP(INDEX_op_extract_i64, TCGOutOpExtract, outop_extract),
OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond),
OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2),
@ -5511,6 +5519,18 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
break;
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
{
const TCGOutOpExtract *out =
container_of(all_outop[op->opc], TCGOutOpExtract, base);
tcg_debug_assert(!const_args[1]);
out->out_rr(s, type, new_args[0], new_args[1],
new_args[2], new_args[3]);
}
break;
case INDEX_op_muls2:
case INDEX_op_mulu2:
{

8
tcg/tci/tcg-target.c.inc
View file

@ -57,8 +57,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
return C_O1_I1(r, r);
@ -444,6 +442,11 @@ static void tcg_out_extract(TCGContext *s, TCGType type, TCGReg rd,
tcg_out_op_rrbb(s, opc, rd, rs, pos, len);
}
static const TCGOutOpExtract outop_extract = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tcg_out_extract,
};
static void tcg_out_sextract(TCGContext *s, TCGType type, TCGReg rd,
TCGReg rs, unsigned pos, unsigned len)
{
@ -1078,7 +1081,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], args[3], args[4]);
break;
CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */
CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
tcg_out_op_rrbb(s, opc, args[0], args[1], args[2], args[3]);
break;