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tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64
Even though bswap64 can only be used with TCG_TYPE_I64, rename the opcode to maintain uniformity. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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7 changed files with 15 additions and 15 deletions
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@ -431,10 +431,11 @@ Misc
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they apply from bit 31 instead of bit 15. On TCG_TYPE_I32, the
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flags should be zero.
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* - bswap64_i64 *t0*, *t1*, *flags*
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* - bswap64 *t0*, *t1*, *flags*
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- | 64 bit byte swap. The flags are ignored, but still present
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for consistency with the other bswap opcodes.
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for consistency with the other bswap opcodes. For future
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compatibility, the flags should be zero.
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* - discard_i32/i64 *t0*
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@ -45,6 +45,7 @@ DEF(and, 1, 2, 0, TCG_OPF_INT)
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DEF(andc, 1, 2, 0, TCG_OPF_INT)
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DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
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DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
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DEF(bswap64, 1, 1, 1, TCG_OPF_INT)
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DEF(clz, 1, 2, 0, TCG_OPF_INT)
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DEF(ctpop, 1, 1, 0, TCG_OPF_INT)
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DEF(ctz, 1, 2, 0, TCG_OPF_INT)
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@ -121,8 +122,6 @@ DEF(extu_i32_i64, 1, 1, 0, 0)
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DEF(extrl_i64_i32, 1, 1, 0, 0)
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DEF(extrh_i64_i32, 1, 1, 0, 0)
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DEF(bswap64_i64, 1, 1, 1, 0)
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DEF(add2_i64, 2, 4, 0, 0)
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DEF(sub2_i64, 2, 4, 0, 0)
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@ -526,7 +526,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
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x = bswap32(x);
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return y & TCG_BSWAP_OS ? (int32_t)x : x;
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64:
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return bswap64(x);
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case INDEX_op_ext_i32_i64:
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@ -1580,7 +1580,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
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z_mask = bswap32(z_mask);
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sign = INT32_MIN;
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break;
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64:
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z_mask = bswap64(z_mask);
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sign = INT64_MIN;
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break;
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@ -2870,7 +2870,7 @@ void tcg_optimize(TCGContext *s)
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break;
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case INDEX_op_bswap16:
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case INDEX_op_bswap32:
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64:
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done = fold_bswap(&ctx, op);
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break;
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case INDEX_op_clz:
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@ -2184,8 +2184,8 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
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tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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} else if (tcg_op_supported(INDEX_op_bswap64_i64, TCG_TYPE_I64, 0)) {
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tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0);
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} else if (tcg_op_supported(INDEX_op_bswap64, TCG_TYPE_I64, 0)) {
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tcg_gen_op3i_i64(INDEX_op_bswap64, ret, arg, 0);
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} else {
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TCGv_i64 t0 = tcg_temp_ebb_new_i64();
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TCGv_i64 t1 = tcg_temp_ebb_new_i64();
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@ -1113,7 +1113,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
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OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2),
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OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2),
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#else
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OUTOP(INDEX_op_bswap64_i64, TCGOutOpUnary, outop_bswap64),
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OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64),
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#endif
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};
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@ -2939,7 +2939,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
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break;
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case INDEX_op_bswap16:
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case INDEX_op_bswap32:
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64:
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{
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TCGArg flags = op->args[k];
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const char *name = NULL;
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@ -5470,7 +5470,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
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}
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break;
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64:
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assert(TCG_TARGET_REG_BITS == 64);
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/* fall through */
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case INDEX_op_ctpop:
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@ -788,7 +788,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = (uint32_t)regs[r1];
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break;
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64:
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = bswap64(regs[r1]);
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break;
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@ -1009,7 +1009,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
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case INDEX_op_not:
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case INDEX_op_ext_i32_i64:
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case INDEX_op_extu_i32_i64:
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64:
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tci_args_rr(insn, &r0, &r1);
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info->fprintf_func(info->stream, "%-12s %s, %s",
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op_name, str_r(r0), str_r(r1));
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@ -930,7 +930,7 @@ static const TCGOutOpBswap outop_bswap32 = {
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#if TCG_TARGET_REG_BITS == 64
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static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
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{
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tcg_out_op_rr(s, INDEX_op_bswap64_i64, a0, a1);
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tcg_out_op_rr(s, INDEX_op_bswap64, a0, a1);
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}
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static const TCGOutOpUnary outop_bswap64 = {
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