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tcg: Convert not to TCGOutOpUnary

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 23:37:54 -08:00
parent 6971358747
commit 592982bf04
25 changed files with 119 additions and 103 deletions
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2
tcg/aarch64/tcg-target-has.h
View file

@ -17,7 +17,6 @@
#define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1
@ -38,7 +37,6 @@
#define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1

17
tcg/aarch64/tcg-target.c.inc
View file

@ -2245,6 +2245,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_orc(s, type, a0, TCG_REG_XZR, a1);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2312,11 +2322,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3); tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
break; break;
case INDEX_op_not_i64:
case INDEX_op_not_i32:
tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1);
break;
case INDEX_op_mul_i64: case INDEX_op_mul_i64:
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR); tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR);
@ -2996,8 +3001,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_bswap16_i64: case INDEX_op_bswap16_i64:

1
tcg/arm/tcg-target-has.h
View file

@ -26,7 +26,6 @@ extern bool use_neon_instructions;
/* optional instructions */ /* optional instructions */
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions

15
tcg/arm/tcg-target.c.inc
View file

@ -1961,6 +1961,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0));
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2050,10 +2060,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
tcg_out_mov_reg(s, COND_AL, args[0], a0); tcg_out_mov_reg(s, COND_AL, args[0], a0);
break; break;
case INDEX_op_not_i32:
tcg_out_dat_reg(s, COND_AL,
ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
break;
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
break; break;
@ -2233,7 +2239,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32: case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32: case INDEX_op_ld_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:

2
tcg/i386/tcg-target-has.h
View file

@ -30,7 +30,6 @@
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1
#define TCG_TARGET_HAS_ctpop_i32 have_popcnt #define TCG_TARGET_HAS_ctpop_i32 have_popcnt
@ -51,7 +50,6 @@
#define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1
#define TCG_TARGET_HAS_ctpop_i64 have_popcnt #define TCG_TARGET_HAS_ctpop_i64 have_popcnt

17
tcg/i386/tcg-target.c.inc
View file

@ -2712,6 +2712,17 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, 0),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2911,10 +2922,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
OP_32_64(not):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
break;
case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32); tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32);
break; break;
@ -3727,8 +3734,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64: case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:
return C_O1_I1(r, 0); return C_O1_I1(r, 0);

2
tcg/loongarch64/tcg-target-has.h
View file

@ -24,7 +24,6 @@
#define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1
#define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0
@ -41,7 +40,6 @@
#define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1
#define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0

17
tcg/loongarch64/tcg-target.c.inc
View file

@ -1419,6 +1419,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_nor(s, type, a0, a1, TCG_REG_ZERO);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1454,11 +1464,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_srai_d(s, a0, a1, 32); tcg_out_opc_srai_d(s, a0, a1, 32);
break; break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
break;
case INDEX_op_extract_i32: case INDEX_op_extract_i32:
if (a2 == 0 && args[3] <= 12) { if (a2 == 0 && args[3] <= 12) {
tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1); tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1);
@ -2275,8 +2280,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extrl_i64_i32: case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:
case INDEX_op_extract_i64: case INDEX_op_extract_i64:
case INDEX_op_sextract_i32: case INDEX_op_sextract_i32:

2
tcg/mips/tcg-target-has.h
View file

@ -41,7 +41,6 @@ extern bool use_mips32r2_instructions;
/* optional instructions */ /* optional instructions */
#define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions) #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions) #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_muluh_i32 1
@ -56,7 +55,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions) #define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)

20
tcg/mips/tcg-target.c.inc
View file

@ -1793,6 +1793,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_nor(s, type, a0, TCG_REG_ZERO, a1);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1985,14 +1995,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
break; break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
i1 = OPC_NOR;
goto do_unary;
do_unary:
tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
break;
case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64: case INDEX_op_bswap16_i64:
tcg_out_bswap16(s, a0, a1, a2); tcg_out_bswap16(s, a0, a1, a2);
@ -2199,7 +2201,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32: case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32: case INDEX_op_ld_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:
@ -2211,7 +2212,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_not_i64:
case INDEX_op_bswap16_i64: case INDEX_op_bswap16_i64:
case INDEX_op_bswap32_i64: case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:

4
tcg/optimize.c
View file

@ -1104,11 +1104,11 @@ static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx)
switch (ctx->type) { switch (ctx->type) {
case TCG_TYPE_I32: case TCG_TYPE_I32:
not_op = INDEX_op_not_i32; not_op = INDEX_op_not_i32;
have_not = TCG_TARGET_HAS_not_i32; have_not = tcg_op_supported(INDEX_op_not_i32, TCG_TYPE_I32, 0);
break; break;
case TCG_TYPE_I64: case TCG_TYPE_I64:
not_op = INDEX_op_not_i64; not_op = INDEX_op_not_i64;
have_not = TCG_TARGET_HAS_not_i64; have_not = tcg_op_supported(INDEX_op_not_i64, TCG_TYPE_I64, 0);
break; break;
case TCG_TYPE_V64: case TCG_TYPE_V64:
case TCG_TYPE_V128: case TCG_TYPE_V128:

2
tcg/ppc/tcg-target-has.h
View file

@ -22,7 +22,6 @@
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00
#define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06
@ -44,7 +43,6 @@
#define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00
#define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06

17
tcg/ppc/tcg-target.c.inc
View file

@ -3062,6 +3062,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_nor(s, type, a0, a1, a1);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -3234,11 +3244,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_brcond2(s, args, const_args); tcg_out_brcond2(s, args, const_args);
break; break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
break;
case INDEX_op_shl_i64: case INDEX_op_shl_i64:
if (const_args[2]) { if (const_args[2]) {
/* Limit immediate shift count lest we create an illegal insn. */ /* Limit immediate shift count lest we create an illegal insn. */
@ -4124,7 +4129,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16s_i32: case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32: case INDEX_op_ld_i32:
case INDEX_op_ctpop_i32: case INDEX_op_ctpop_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:
@ -4137,7 +4141,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_ctpop_i64: case INDEX_op_ctpop_i64:
case INDEX_op_not_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_bswap16_i64: case INDEX_op_bswap16_i64:

2
tcg/riscv/tcg-target-has.h
View file

@ -24,7 +24,6 @@
#define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB)
@ -40,7 +39,6 @@
#define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB)

17
tcg/riscv/tcg-target.c.inc
View file

@ -2087,6 +2087,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_xori(s, type, a0, a1, -1);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2150,11 +2160,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, OPC_SD, a0, a1, a2); tcg_out_ldst(s, OPC_SD, a0, a1, a2);
break; break;
case INDEX_op_not_i32:
case INDEX_op_not_i64:
tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
break;
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2); tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
break; break;
@ -2662,7 +2667,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32: case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32: case INDEX_op_ld_i32:
case INDEX_op_not_i32:
case INDEX_op_ld8u_i64: case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64: case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i64: case INDEX_op_ld16u_i64:
@ -2670,7 +2674,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_not_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32: case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:

2
tcg/s390x/tcg-target-has.h
View file

@ -33,7 +33,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0
#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_ctpop_i32 1
@ -53,7 +52,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_ctpop_i64 1

25
tcg/s390x/tcg-target.c.inc
View file

@ -2387,6 +2387,22 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_nor(s, type, a0, a1, a1);
}
static TCGConstraintSetIndex cset_not(TCGType type, unsigned flags)
{
return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I1(r, r) : C_NotImplemented;
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_not,
.out_rr = tgen_not,
};
# define OP_32_64(x) \ # define OP_32_64(x) \
case glue(glue(INDEX_op_,x),_i32): \ case glue(glue(INDEX_op_,x),_i32): \
@ -2444,10 +2460,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
break; break;
case INDEX_op_not_i32:
tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]);
break;
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
if (const_args[2]) { if (const_args[2]) {
@ -2635,9 +2647,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
break; break;
case INDEX_op_not_i64:
tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]);
break;
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:
tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
break; break;
@ -3331,8 +3340,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64: case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32: case INDEX_op_extract_i32:

2
tcg/sparc64/tcg-target-has.h
View file

@ -19,7 +19,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_rot_i32 0
#define TCG_TARGET_HAS_bswap16_i32 0 #define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0 #define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0
#define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0
@ -40,7 +39,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap16_i64 0 #define TCG_TARGET_HAS_bswap16_i64 0
#define TCG_TARGET_HAS_bswap32_i64 0 #define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0 #define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0

20
tcg/sparc64/tcg-target.c.inc
View file

@ -1413,6 +1413,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_orc(s, type, a0, TCG_REG_G0, a1);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1483,10 +1493,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
c = ARITH_UMUL; c = ARITH_UMUL;
goto gen_arith; goto gen_arith;
OP_32_64(not):
c = ARITH_ORN;
goto gen_arith1;
case INDEX_op_div_i32: case INDEX_op_div_i32:
tcg_out_div32(s, a0, a1, a2, c2, 0); tcg_out_div32(s, a0, a1, a2, c2, 0);
break; break;
@ -1600,10 +1606,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_arithc(s, a0, a1, a2, c2, c); tcg_out_arithc(s, a0, a1, a2, c2, c);
break; break;
gen_arith1:
tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
break;
case INDEX_op_mb: case INDEX_op_mb:
tcg_out_mb(s, a0); tcg_out_mb(s, a0);
break; break;
@ -1646,8 +1648,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i64: case INDEX_op_extract_i64:

1
tcg/tcg-has.h
View file

@ -19,7 +19,6 @@
#define TCG_TARGET_HAS_bswap16_i64 0 #define TCG_TARGET_HAS_bswap16_i64 0
#define TCG_TARGET_HAS_bswap32_i64 0 #define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0 #define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 0
#define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0

10
tcg/tcg-op.c
View file

@ -461,7 +461,8 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
/* Some cases can be optimized here. */ /* Some cases can be optimized here. */
if (arg2 == 0) { if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1); tcg_gen_mov_i32(ret, arg1);
} else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) { } else if (arg2 == -1 &&
tcg_op_supported(INDEX_op_not_i32, TCG_TYPE_I32, 0)) {
/* Don't recurse with tcg_gen_not_i32. */ /* Don't recurse with tcg_gen_not_i32. */
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1); tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
} else { } else {
@ -471,7 +472,7 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
{ {
if (TCG_TARGET_HAS_not_i32) { if (tcg_op_supported(INDEX_op_not_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
} else { } else {
tcg_gen_xori_i32(ret, arg, -1); tcg_gen_xori_i32(ret, arg, -1);
@ -1762,7 +1763,8 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
/* Some cases can be optimized here. */ /* Some cases can be optimized here. */
if (arg2 == 0) { if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1); tcg_gen_mov_i64(ret, arg1);
} else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) { } else if (arg2 == -1 &&
tcg_op_supported(INDEX_op_not_i64, TCG_TYPE_I64, 0)) {
/* Don't recurse with tcg_gen_not_i64. */ /* Don't recurse with tcg_gen_not_i64. */
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1); tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
} else { } else {
@ -2252,7 +2254,7 @@ void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
if (TCG_TARGET_REG_BITS == 32) { if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
} else if (TCG_TARGET_HAS_not_i64) { } else if (tcg_op_supported(INDEX_op_not_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
} else { } else {
tcg_gen_xori_i64(ret, arg, -1); tcg_gen_xori_i64(ret, arg, -1);

8
tcg/tcg.c
View file

@ -1024,6 +1024,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand), OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg), OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor), OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
OUTOP(INDEX_op_not_i32, TCGOutOpUnary, outop_not),
OUTOP(INDEX_op_not_i64, TCGOutOpUnary, outop_not),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc), OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub), OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
@ -2287,8 +2289,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap16_i32; return TCG_TARGET_HAS_bswap16_i32;
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
return TCG_TARGET_HAS_bswap32_i32; return TCG_TARGET_HAS_bswap32_i32;
case INDEX_op_not_i32:
return TCG_TARGET_HAS_not_i32;
case INDEX_op_clz_i32: case INDEX_op_clz_i32:
return TCG_TARGET_HAS_clz_i32; return TCG_TARGET_HAS_clz_i32;
case INDEX_op_ctz_i32: case INDEX_op_ctz_i32:
@ -2350,8 +2350,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap32_i64; return TCG_TARGET_HAS_bswap32_i64;
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:
return TCG_TARGET_HAS_bswap64_i64; return TCG_TARGET_HAS_bswap64_i64;
case INDEX_op_not_i64:
return TCG_TARGET_HAS_not_i64;
case INDEX_op_clz_i64: case INDEX_op_clz_i64:
return TCG_TARGET_HAS_clz_i64; return TCG_TARGET_HAS_clz_i64;
case INDEX_op_ctz_i64: case INDEX_op_ctz_i64:
@ -5476,6 +5474,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
break; break;
case INDEX_op_neg: case INDEX_op_neg:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
{ {
const TCGOutOpUnary *out = const TCGOutOpUnary *out =
container_of(all_outop[op->opc], TCGOutOpUnary, base); container_of(all_outop[op->opc], TCGOutOpUnary, base);

2
tcg/tci.c
View file

@ -695,12 +695,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
regs[r0] = bswap32(regs[r1]); regs[r0] = bswap32(regs[r1]);
break; break;
#endif #endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not) CASE_32_64(not)
tci_args_rr(insn, &r0, &r1); tci_args_rr(insn, &r0, &r1);
regs[r0] = ~regs[r1]; regs[r0] = ~regs[r1];
break; break;
#endif
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
/* Load/store operations (64 bit). */ /* Load/store operations (64 bit). */

2
tcg/tci/tcg-target-has.h
View file

@ -15,7 +15,6 @@
#define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1
#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_ctpop_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_negsetcond_i32 0
#define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muls2_i32 1
@ -34,7 +33,6 @@
#define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1
#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_ctpop_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 0
#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_muls2_i64 1

13
tcg/tci/tcg-target.c.inc
View file

@ -55,8 +55,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i32:
@ -739,6 +737,16 @@ static const TCGOutOpUnary outop_neg = {
.out_rr = tgen_neg, .out_rr = tgen_neg,
}; };
static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_op_rr(s, glue(INDEX_op_not_i,TCG_TARGET_REG_BITS), a0, a1);
}
static const TCGOutOpUnary outop_not = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_not,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -812,7 +820,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3])); tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3]));
break; break;
CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */
case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */