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hw/intc/aspeed: Add object type name to trace events for better debugging

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Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.

However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds object type name
to the INTC trace events.
Update trace events to include the "name" field for better identification.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-8-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:16 +08:00 • committed by Cédric Le Goater
parent 3d6e15eafb
commit 49da40cf5f
2 changed files with 31 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

32
hw/intc/aspeed_intc.c
View file

@ -45,6 +45,7 @@ REG32(GICINT136_STATUS, 0x804)
static void aspeed_intc_update(AspeedINTCState *s, int irq, int level) static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
{ {
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
if (irq >= aic->num_ints) { if (irq >= aic->num_ints) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
@ -52,7 +53,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
return; return;
} }
trace_aspeed_intc_update_irq(irq, level); trace_aspeed_intc_update_irq(name, irq, level);
qemu_set_irq(s->output_pins[irq], level); qemu_set_irq(s->output_pins[irq], level);
} }
@ -66,6 +67,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
{ {
AspeedINTCState *s = (AspeedINTCState *)opaque; AspeedINTCState *s = (AspeedINTCState *)opaque;
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
uint32_t status_reg = GICINT_STATUS_BASE + ((0x100 * irq) >> 2); uint32_t status_reg = GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
uint32_t select = 0; uint32_t select = 0;
uint32_t enable; uint32_t enable;
@ -77,7 +79,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
return; return;
} }
trace_aspeed_intc_set_irq(irq, level); trace_aspeed_intc_set_irq(name, irq, level);
enable = s->enable[irq]; enable = s->enable[irq];
if (!level) { if (!level) {
@ -96,7 +98,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
return; return;
} }
trace_aspeed_intc_select(select); trace_aspeed_intc_select(name, select);
if (s->mask[irq] || s->regs[status_reg]) { if (s->mask[irq] || s->regs[status_reg]) {
/* /*
@ -108,14 +110,14 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
* save source interrupt to pending variable. * save source interrupt to pending variable.
*/ */
s->pending[irq] |= select; s->pending[irq] |= select;
trace_aspeed_intc_pending_irq(irq, s->pending[irq]); trace_aspeed_intc_pending_irq(name, irq, s->pending[irq]);
} else { } else {
/* /*
* notify firmware which source interrupt are coming * notify firmware which source interrupt are coming
* by setting status register * by setting status register
*/ */
s->regs[status_reg] = select; s->regs[status_reg] = select;
trace_aspeed_intc_trigger_irq(irq, s->regs[status_reg]); trace_aspeed_intc_trigger_irq(name, irq, s->regs[status_reg]);
aspeed_intc_update(s, irq, 1); aspeed_intc_update(s, irq, 1);
} }
} }
@ -124,6 +126,7 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
uint64_t data) uint64_t data)
{ {
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
uint32_t reg = offset >> 2; uint32_t reg = offset >> 2;
uint32_t old_enable; uint32_t old_enable;
uint32_t change; uint32_t change;
@ -154,7 +157,7 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
/* enable new source interrupt */ /* enable new source interrupt */
if (old_enable != s->enable[irq]) { if (old_enable != s->enable[irq]) {
trace_aspeed_intc_enable(s->enable[irq]); trace_aspeed_intc_enable(name, s->enable[irq]);
s->regs[reg] = data; s->regs[reg] = data;
return; return;
} }
@ -163,10 +166,10 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
change = s->regs[reg] ^ data; change = s->regs[reg] ^ data;
if (change & data) { if (change & data) {
s->mask[irq] &= ~change; s->mask[irq] &= ~change;
trace_aspeed_intc_unmask(change, s->mask[irq]); trace_aspeed_intc_unmask(name, change, s->mask[irq]);
} else { } else {
s->mask[irq] |= change; s->mask[irq] |= change;
trace_aspeed_intc_mask(change, s->mask[irq]); trace_aspeed_intc_mask(name, change, s->mask[irq]);
} }
s->regs[reg] = data; s->regs[reg] = data;
@ -176,6 +179,7 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
uint64_t data) uint64_t data)
{ {
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
uint32_t reg = offset >> 2; uint32_t reg = offset >> 2;
uint32_t irq; uint32_t irq;
@ -207,7 +211,7 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
/* All source ISR execution are done */ /* All source ISR execution are done */
if (!s->regs[reg]) { if (!s->regs[reg]) {
trace_aspeed_intc_all_isr_done(irq); trace_aspeed_intc_all_isr_done(name, irq);
if (s->pending[irq]) { if (s->pending[irq]) {
/* /*
* handle pending source interrupt * handle pending source interrupt
@ -216,11 +220,11 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
*/ */
s->regs[reg] = s->pending[irq]; s->regs[reg] = s->pending[irq];
s->pending[irq] = 0; s->pending[irq] = 0;
trace_aspeed_intc_trigger_irq(irq, s->regs[reg]); trace_aspeed_intc_trigger_irq(name, irq, s->regs[reg]);
aspeed_intc_update(s, irq, 1); aspeed_intc_update(s, irq, 1);
} else { } else {
/* clear irq */ /* clear irq */
trace_aspeed_intc_clear_irq(irq, 0); trace_aspeed_intc_clear_irq(name, irq, 0);
aspeed_intc_update(s, irq, 0); aspeed_intc_update(s, irq, 0);
} }
} }
@ -229,11 +233,12 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size) static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
{ {
AspeedINTCState *s = ASPEED_INTC(opaque); AspeedINTCState *s = ASPEED_INTC(opaque);
const char *name = object_get_typename(OBJECT(s));
uint32_t reg = offset >> 2; uint32_t reg = offset >> 2;
uint32_t value = 0; uint32_t value = 0;
value = s->regs[reg]; value = s->regs[reg];
trace_aspeed_intc_read(offset, size, value); trace_aspeed_intc_read(name, offset, size, value);
return value; return value;
} }
@ -242,9 +247,10 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size) unsigned size)
{ {
AspeedINTCState *s = ASPEED_INTC(opaque); AspeedINTCState *s = ASPEED_INTC(opaque);
const char *name = object_get_typename(OBJECT(s));
uint32_t reg = offset >> 2; uint32_t reg = offset >> 2;
trace_aspeed_intc_write(offset, size, data); trace_aspeed_intc_write(name, offset, size, data);
switch (reg) { switch (reg) {
case R_GICINT128_EN: case R_GICINT128_EN:

24
hw/intc/trace-events
View file

@ -80,18 +80,18 @@ aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
# aspeed_intc.c # aspeed_intc.c
aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 aspeed_intc_read(const char *s, uint64_t offset, unsigned size, uint32_t value) "%s: From 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 aspeed_intc_write(const char *s, uint64_t offset, unsigned size, uint32_t data) "%s: To 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_intc_set_irq(int irq, int level) "Set IRQ %d: %d" aspeed_intc_set_irq(const char *s, int irq, int level) "%s: Set IRQ %d: %d"
aspeed_intc_clear_irq(int irq, int level) "Clear IRQ %d: %d" aspeed_intc_clear_irq(const char *s, int irq, int level) "%s: Clear IRQ %d: %d"
aspeed_intc_update_irq(int irq, int level) "Update IRQ: %d: %d" aspeed_intc_update_irq(const char *s, int irq, int level) "%s: Update IRQ: %d: %d"
aspeed_intc_pending_irq(int irq, uint32_t value) "Pending IRQ: %d: 0x%x" aspeed_intc_pending_irq(const char *s, int irq, uint32_t value) "%s: Pending IRQ: %d: 0x%x"
aspeed_intc_trigger_irq(int irq, uint32_t value) "Trigger IRQ: %d: 0x%x" aspeed_intc_trigger_irq(const char *s, int irq, uint32_t value) "%s: Trigger IRQ: %d: 0x%x"
aspeed_intc_all_isr_done(int irq) "All source ISR execution are done: %d" aspeed_intc_all_isr_done(const char *s, int irq) "%s: All source ISR execution are done: %d"
aspeed_intc_enable(uint32_t value) "Enable: 0x%x" aspeed_intc_enable(const char *s, uint32_t value) "%s: Enable: 0x%x"
aspeed_intc_select(uint32_t value) "Select: 0x%x" aspeed_intc_select(const char *s, uint32_t value) "%s: Select: 0x%x"
aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x" aspeed_intc_mask(const char *s, uint32_t change, uint32_t value) "%s: Mask: 0x%x: 0x%x"
aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x" aspeed_intc_unmask(const char *s, uint32_t change, uint32_t value) "%s: UnMask: 0x%x: 0x%x"
# arm_gic.c # arm_gic.c
gic_enable_irq(int irq) "irq %d enabled" gic_enable_irq(int irq) "irq %d enabled"