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hw/intc/aspeed: Introduce helper functions for enable and status registers
The behavior of the enable and status registers is almost identical between INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds "aspeed_intc_enable_handler" functions to handle enable register write behavior and "aspeed_intc_status_handler" functions to handle status register write behavior. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin
Cédric Le Goater
parent
7ffee511fc
commit
3d6e15eafb
1 changed files with 108 additions and 83 deletions
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@ -120,6 +120,112 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
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}
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}
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static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
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uint64_t data)
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{
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AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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uint32_t reg = offset >> 2;
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uint32_t old_enable;
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uint32_t change;
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uint32_t irq;
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irq = (offset & 0x0f00) >> 8;
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if (irq >= aic->num_ints) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
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__func__, irq);
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return;
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}
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/*
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* The enable registers are used to enable source interrupts.
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* They also handle masking and unmasking of source interrupts
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* during the execution of the source ISR.
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*/
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/* disable all source interrupt */
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if (!data && !s->enable[irq]) {
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s->regs[reg] = data;
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return;
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}
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old_enable = s->enable[irq];
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s->enable[irq] |= data;
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/* enable new source interrupt */
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if (old_enable != s->enable[irq]) {
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trace_aspeed_intc_enable(s->enable[irq]);
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s->regs[reg] = data;
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return;
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}
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/* mask and unmask source interrupt */
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change = s->regs[reg] ^ data;
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if (change & data) {
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s->mask[irq] &= ~change;
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trace_aspeed_intc_unmask(change, s->mask[irq]);
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} else {
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s->mask[irq] |= change;
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trace_aspeed_intc_mask(change, s->mask[irq]);
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}
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s->regs[reg] = data;
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}
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static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
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uint64_t data)
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{
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AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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uint32_t reg = offset >> 2;
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uint32_t irq;
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if (!data) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
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return;
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}
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irq = (offset & 0x0f00) >> 8;
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if (irq >= aic->num_ints) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
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__func__, irq);
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return;
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}
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/* clear status */
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s->regs[reg] &= ~data;
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/*
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* These status registers are used for notify sources ISR are executed.
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* If one source ISR is executed, it will clear one bit.
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* If it clear all bits, it means to initialize this register status
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* rather than sources ISR are executed.
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*/
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if (data == 0xffffffff) {
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return;
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}
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/* All source ISR execution are done */
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if (!s->regs[reg]) {
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trace_aspeed_intc_all_isr_done(irq);
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if (s->pending[irq]) {
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/*
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* handle pending source interrupt
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* notify firmware which source interrupt are pending
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* by setting status register
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*/
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s->regs[reg] = s->pending[irq];
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s->pending[irq] = 0;
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trace_aspeed_intc_trigger_irq(irq, s->regs[reg]);
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aspeed_intc_update(s, irq, 1);
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} else {
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/* clear irq */
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trace_aspeed_intc_clear_irq(irq, 0);
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aspeed_intc_update(s, irq, 0);
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}
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}
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}
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static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
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{
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AspeedINTCState *s = ASPEED_INTC(opaque);
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@ -136,11 +242,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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AspeedINTCState *s = ASPEED_INTC(opaque);
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AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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uint32_t reg = offset >> 2;
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uint32_t old_enable;
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uint32_t change;
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uint32_t irq;
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trace_aspeed_intc_write(offset, size, data);
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@ -154,45 +256,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
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case R_GICINT134_EN:
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case R_GICINT135_EN:
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case R_GICINT136_EN:
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irq = (offset & 0x0f00) >> 8;
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if (irq >= aic->num_ints) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
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__func__, irq);
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return;
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}
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/*
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* These registers are used for enable sources interrupt and
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* mask and unmask source interrupt while executing source ISR.
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*/
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/* disable all source interrupt */
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if (!data && !s->enable[irq]) {
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s->regs[reg] = data;
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return;
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}
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old_enable = s->enable[irq];
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s->enable[irq] |= data;
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/* enable new source interrupt */
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if (old_enable != s->enable[irq]) {
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trace_aspeed_intc_enable(s->enable[irq]);
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s->regs[reg] = data;
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return;
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}
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/* mask and unmask source interrupt */
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change = s->regs[reg] ^ data;
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if (change & data) {
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s->mask[irq] &= ~change;
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trace_aspeed_intc_unmask(change, s->mask[irq]);
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} else {
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s->mask[irq] |= change;
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trace_aspeed_intc_mask(change, s->mask[irq]);
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}
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s->regs[reg] = data;
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aspeed_intc_enable_handler(s, offset, data);
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break;
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case R_GICINT128_STATUS:
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case R_GICINT129_STATUS:
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@ -203,46 +267,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
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case R_GICINT134_STATUS:
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case R_GICINT135_STATUS:
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case R_GICINT136_STATUS:
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irq = (offset & 0x0f00) >> 8;
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if (irq >= aic->num_ints) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
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__func__, irq);
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return;
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}
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/* clear status */
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s->regs[reg] &= ~data;
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/*
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* These status registers are used for notify sources ISR are executed.
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* If one source ISR is executed, it will clear one bit.
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* If it clear all bits, it means to initialize this register status
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* rather than sources ISR are executed.
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*/
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if (data == 0xffffffff) {
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return;
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}
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/* All source ISR execution are done */
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if (!s->regs[reg]) {
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trace_aspeed_intc_all_isr_done(irq);
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if (s->pending[irq]) {
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/*
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* handle pending source interrupt
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* notify firmware which source interrupt are pending
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* by setting status register
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*/
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s->regs[reg] = s->pending[irq];
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s->pending[irq] = 0;
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trace_aspeed_intc_trigger_irq(irq, s->regs[reg]);
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aspeed_intc_update(s, irq, 1);
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} else {
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/* clear irq */
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trace_aspeed_intc_clear_irq(irq, 0);
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aspeed_intc_update(s, irq, 0);
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}
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}
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aspeed_intc_status_handler(s, offset, data);
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break;
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default:
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s->regs[reg] = data;
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