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hw/misc: Add a basic Aspeed LPC controller model

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This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater 2021-03-09 12:01:28 +01:00
parent 6820588efa
commit 2ecf17264d
7 changed files with 192 additions and 2 deletions
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32
include/hw/misc/aspeed_lpc.h Normal file
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/*
* ASPEED LPC Controller
*
* Copyright (C) 2017-2018 IBM Corp.
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*/
#ifndef ASPEED_LPC_H
#define ASPEED_LPC_H
#include "hw/sysbus.h"
#define TYPE_ASPEED_LPC "aspeed.lpc"
#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC)
#define ASPEED_LPC_NR_REGS (0x260 >> 2)
typedef struct AspeedLPCState {
/* <private> */
SysBusDevice parent;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
uint32_t regs[ASPEED_LPC_NR_REGS];
uint32_t hicr7;
} AspeedLPCState;
#endif /* _ASPEED_LPC_H_ */