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This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
32 lines
659 B
C
32 lines
659 B
C
/*
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* ASPEED LPC Controller
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*
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* Copyright (C) 2017-2018 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_LPC_H
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#define ASPEED_LPC_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_LPC "aspeed.lpc"
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#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC)
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#define ASPEED_LPC_NR_REGS (0x260 >> 2)
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typedef struct AspeedLPCState {
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/* <private> */
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SysBusDevice parent;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t regs[ASPEED_LPC_NR_REGS];
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uint32_t hicr7;
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} AspeedLPCState;
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#endif /* _ASPEED_LPC_H_ */
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