motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-07-27 04:13:53 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst

Browse source 
There is now always only one guest address register.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-04 18:08:19 -08:00
parent 7a967f3466
commit 0cd38379a8
10 changed files with 27 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tcg/aarch64/tcg-target.c.inc
View file

@ -1775,7 +1775,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
mask_type = (s->page_bits + s->tlb_dyn_max_bits > 32 mask_type = (s->page_bits + s->tlb_dyn_max_bits > 32
? TCG_TYPE_I64 : TCG_TYPE_I32); ? TCG_TYPE_I64 : TCG_TYPE_I32);
@ -1837,7 +1837,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
/* tst addr, #mask */ /* tst addr, #mask */
tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);

4
tcg/arm/tcg-target.c.inc
View file

@ -1485,7 +1485,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
@ -1552,7 +1552,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
/* We are expecting alignment to max out at 7 */ /* We are expecting alignment to max out at 7 */
tcg_debug_assert(a_mask <= 0xff); tcg_debug_assert(a_mask <= 0xff);

4
tcg/i386/tcg-target.c.inc
View file

@ -2201,7 +2201,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
ttype = s->addr_type; ttype = s->addr_type;
@ -2257,7 +2257,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
/* jne slow_path */ /* jne slow_path */
jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false); jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false);

4
tcg/loongarch64/tcg-target.c.inc
View file

@ -1010,7 +1010,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
@ -1055,7 +1055,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
/* /*
* Without micro-architecture details, we don't know which of * Without micro-architecture details, we don't know which of

4
tcg/mips/tcg-target.c.inc
View file

@ -1244,7 +1244,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
@ -1309,7 +1309,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
/* We are expecting a_bits to max out at 7, much lower than ANDI. */ /* We are expecting a_bits to max out at 7, much lower than ANDI. */
tcg_debug_assert(a_bits < 16); tcg_debug_assert(a_bits < 16);

4
tcg/ppc/tcg-target.c.inc
View file

@ -2473,7 +2473,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
@ -2577,7 +2577,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr; ldst->addr_reg = addr;
/* We are expecting a_bits to max out at 7, much lower than ANDI. */ /* We are expecting a_bits to max out at 7, much lower than ANDI. */
tcg_debug_assert(a_bits < 16); tcg_debug_assert(a_bits < 16);

4
tcg/riscv/tcg-target.c.inc
View file

@ -1727,7 +1727,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
init_setting_vtype(s); init_setting_vtype(s);
@ -1790,7 +1790,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
init_setting_vtype(s); init_setting_vtype(s);

4
tcg/s390x/tcg-target.c.inc
View file

@ -1920,7 +1920,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE,
s->page_bits - CPU_TLB_ENTRY_BITS); s->page_bits - CPU_TLB_ENTRY_BITS);
@ -1974,7 +1974,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
tcg_debug_assert(a_mask <= 0xffff); tcg_debug_assert(a_mask <= 0xffff);
tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);

4
tcg/sparc64/tcg-target.c.inc
View file

@ -1127,7 +1127,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
ldst->label_ptr[0] = s->code_ptr; ldst->label_ptr[0] = s->code_ptr;
/* bne,pn %[xi]cc, label0 */ /* bne,pn %[xi]cc, label0 */
@ -1147,7 +1147,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addr_reg; ldst->addr_reg = addr_reg;
ldst->label_ptr[0] = s->code_ptr; ldst->label_ptr[0] = s->code_ptr;
/* bne,pn %icc, label0 */ /* bne,pn %icc, label0 */

18
tcg/tcg.c
View file

@ -100,8 +100,7 @@ struct TCGLabelQemuLdst {
bool is_ld; /* qemu_ld: true, qemu_st: false */ bool is_ld; /* qemu_ld: true, qemu_st: false */
MemOpIdx oi; MemOpIdx oi;
TCGType type; /* result type of a load */ TCGType type; /* result type of a load */
TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */ TCGReg addr_reg; /* reg index for guest virtual addr */
TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ TCGReg datalo_reg; /* reg index for low word to be loaded or stored */
TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ TCGReg datahi_reg; /* reg index for high word to be loaded or stored */
const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */ const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */
@ -6061,7 +6060,7 @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
*/ */
tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN,
TCG_TYPE_I32, TCG_TYPE_I32, TCG_TYPE_I32, TCG_TYPE_I32,
ldst->addrlo_reg, -1); ldst->addr_reg, -1);
tcg_out_helper_load_slots(s, 1, mov, parm); tcg_out_helper_load_slots(s, 1, mov, parm);
tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot,
@ -6069,7 +6068,7 @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
next_arg += 2; next_arg += 2;
} else { } else {
nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type,
ldst->addrlo_reg, ldst->addrhi_reg); ldst->addr_reg, -1);
tcg_out_helper_load_slots(s, nmov, mov, parm); tcg_out_helper_load_slots(s, nmov, mov, parm);
next_arg += nmov; next_arg += nmov;
} }
@ -6226,21 +6225,22 @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
/* Handle addr argument. */ /* Handle addr argument. */
loc = &info->in[next_arg]; loc = &info->in[next_arg];
if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { tcg_debug_assert(s->addr_type <= TCG_TYPE_REG);
if (TCG_TARGET_REG_BITS == 32) {
/* /*
* 32-bit host with 32-bit guest: zero-extend the guest address * 32-bit host (and thus 32-bit guest): zero-extend the guest address
* to 64-bits for the helper by storing the low part. Later, * to 64-bits for the helper by storing the low part. Later,
* after we have processed the register inputs, we will load a * after we have processed the register inputs, we will load a
* zero for the high part. * zero for the high part.
*/ */
tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN,
TCG_TYPE_I32, TCG_TYPE_I32, TCG_TYPE_I32, TCG_TYPE_I32,
ldst->addrlo_reg, -1); ldst->addr_reg, -1);
next_arg += 2; next_arg += 2;
nmov += 1; nmov += 1;
} else { } else {
n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type,
ldst->addrlo_reg, ldst->addrhi_reg); ldst->addr_reg, -1);
next_arg += n; next_arg += n;
nmov += n; nmov += n;
} }
@ -6288,7 +6288,7 @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
g_assert_not_reached(); g_assert_not_reached();
} }
if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { if (TCG_TARGET_REG_BITS == 32) {
/* Zero extend the address by loading a zero for the high part. */ /* Zero extend the address by loading a zero for the high part. */
loc = &info->in[1 + !HOST_BIG_ENDIAN]; loc = &info->in[1 + !HOST_BIG_ENDIAN];
tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm);