mirror of
https://github.com/Motorhead1991/qemu.git
synced 2026-03-17 16:25:34 -06:00
For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know whether the stage 1 access is for EL0 or not, because whether exec permission is given can depend on whether this is an EL0 or EL1 access. Add a new argument to get_phys_addr_lpae() so the call sites can pass this information in. Since get_phys_addr_lpae() doesn't already have a doc comment, add one so we have a place to put the documentation of the semantics of the new s1_is_el0 argument. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200330210400.11724-4-peter.maydell@linaro.org |
||
|---|---|---|
| .. | ||
| alpha | ||
| arm | ||
| cris | ||
| hppa | ||
| i386 | ||
| lm32 | ||
| m68k | ||
| microblaze | ||
| mips | ||
| moxie | ||
| nios2 | ||
| openrisc | ||
| ppc | ||
| riscv | ||
| rx | ||
| s390x | ||
| sh4 | ||
| sparc | ||
| tilegx | ||
| tricore | ||
| unicore32 | ||
| xtensa | ||