Richard Henderson fe0a69cca5 target/hppa: Fix 32-bit operand masks for 0E FCVT ... We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2018-01-31 05:30:50 -08:00
..
cpu-qom.h	target-hppa: Add framework and enable compilation	2017-01-23 09:52:40 -08:00
cpu.c	target/hppa: Add migration for the cpu	2018-01-31 05:30:49 -08:00
cpu.h	target/hppa: Enable MTTCG	2018-01-31 05:30:50 -08:00
gdbstub.c	target/hppa: Add system registers to gdbstub	2018-01-31 05:30:49 -08:00
helper.c	target/hppa: Implement IASQ	2018-01-30 10:08:18 -08:00
helper.h	target/hppa: Implement halt and reset instructions	2018-01-31 05:30:49 -08:00
int_helper.c	target/hppa: Implement the interval timer	2018-01-30 10:22:26 -08:00
machine.c	target/hppa: Add migration for the cpu	2018-01-31 05:30:49 -08:00
Makefile.objs	target/hppa: Add migration for the cpu	2018-01-31 05:30:49 -08:00
mem_helper.c	target/hppa: Only use EXCP_DTLB_MISS	2018-01-31 05:30:50 -08:00
op_helper.c	target/hppa: Implement halt and reset instructions	2018-01-31 05:30:49 -08:00
translate.c	target/hppa: Fix 32-bit operand masks for 0E FCVT	2018-01-31 05:30:50 -08:00