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6effa87475
Don't base the values on TARGET_PAGE_BITS_MIN, but do verify that TLB_FLAGS_MASK does not overlap minimum page size. All targets now have the same placement for these flags, simplifying mmu management when we enable heterogeneous systems. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
86 lines
2.7 KiB
C
86 lines
2.7 KiB
C
/*
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* TLB flags definition
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TLB_FLAGS_H
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#define TLB_FLAGS_H
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/*
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* Flags returned for lookup of a TLB virtual address.
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*/
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#ifdef CONFIG_USER_ONLY
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/*
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* Allow some level of source compatibility with softmmu.
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* Invalid is set when the page does not have requested permissions.
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* MMIO is set when we want the target helper to use the functional
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* interface for load/store so that plugins see the access.
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*/
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#define TLB_INVALID_MASK (1 << 0)
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#define TLB_MMIO (1 << 1)
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#define TLB_WATCHPOINT 0
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#else
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/*
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* Flags stored in CPUTLBEntryFull.slow_flags[x].
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* TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
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*/
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/* Set if TLB entry requires byte swap. */
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#define TLB_BSWAP (1 << 0)
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/* Set if TLB entry contains a watchpoint. */
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#define TLB_WATCHPOINT (1 << 1)
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/* Set if TLB entry requires aligned accesses. */
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#define TLB_CHECK_ALIGNED (1 << 2)
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/* Set if TLB entry writes ignored. */
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#define TLB_DISCARD_WRITE (1 << 3)
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/* Set if TLB entry is an IO callback. */
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#define TLB_MMIO (1 << 4)
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#define TLB_SLOW_FLAGS_MASK \
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(TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED | \
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TLB_DISCARD_WRITE | TLB_MMIO)
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/*
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* Flags stored in CPUTLBEntry.addr_idx[x].
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* These must be above the largest alignment (64 bytes),
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* and below the smallest page size (1024 bytes).
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* This leaves bits [9:6] available for use.
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*/
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/* Zero if TLB entry is valid. */
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#define TLB_INVALID_MASK (1 << 6)
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/* Set if TLB entry references a clean RAM page. */
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#define TLB_NOTDIRTY (1 << 7)
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/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
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#define TLB_FORCE_SLOW (1 << 8)
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/*
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* Use this mask to check interception with an alignment mask
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* in a TCG backend.
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*/
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#define TLB_FLAGS_MASK \
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(TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_FORCE_SLOW)
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/* The two sets of flags must not overlap. */
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QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
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#endif /* !CONFIG_USER_ONLY */
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#endif /* TLB_FLAGS_H */
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