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1cceedd772
Right now, we only allow for writing to memory regions that allow direct access using memcpy etc; all other writes are simply ignored. This implies that debugging guests will not work as expected when writing to MMIO device regions. Let's extend cpu_memory_rw_debug() to write to more memory regions, including MMIO device regions. Reshuffle the condition in memory_access_is_direct() to make it easier to read and add a comment. While this change implies that debug access can now also write to MMIO devices, we now are also permit ELF image loads and similar users of cpu_memory_rw_debug() to write to MMIO devices; currently we ignore these writes. Peter assumes [1] that there's probably a class of guest images, which will start writing junk (likely zeroes) into device model registers; we previously would silently ignore any such bogus ELF sections. Likely these images are of questionable correctness and this can be ignored. If ever a problem, we could make these cases use address_space_write_rom() instead, which is left unchanged for now. This patch is based on previous work by Stefan Zabka. [1] https://lore.kernel.org/all/CAFEAcA_2CEJKFyjvbwmpt=on=GgMVamQ5hiiVt+zUr6AY3X=Xg@mail.gmail.com/ Resolves: https://gitlab.com/qemu-project/qemu/-/issues/213 Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/r/20250210084648.33798-8-david@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com>
90 lines
3 KiB
C
90 lines
3 KiB
C
/*
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* Memory transaction attributes
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*
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* Copyright (c) 2015 Linaro Limited.
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*
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* Authors:
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* Peter Maydell <peter.maydell@linaro.org>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef MEMATTRS_H
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#define MEMATTRS_H
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/* Every memory transaction has associated with it a set of
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* attributes. Some of these are generic (such as the ID of
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* the bus master); some are specific to a particular kind of
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* bus (such as the ARM Secure/NonSecure bit). We define them
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* all as non-overlapping bitfields in a single struct to avoid
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* confusion if different parts of QEMU used the same bit for
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* different semantics.
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*/
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typedef struct MemTxAttrs {
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/*
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* ARM/AMBA: TrustZone Secure access
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* x86: System Management Mode access
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*/
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unsigned int secure:1;
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/*
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* ARM: ArmSecuritySpace. This partially overlaps secure, but it is
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* easier to have both fields to assist code that does not understand
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* ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash).
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*/
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unsigned int space:2;
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/* Memory access is usermode (unprivileged) */
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unsigned int user:1;
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/*
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* Bus interconnect and peripherals can access anything (memories,
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* devices) by default. By setting the 'memory' bit, bus transaction
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* are restricted to "normal" memories (per the AMBA documentation)
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* versus devices. Access to devices will be logged and rejected
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* (see MEMTX_ACCESS_ERROR).
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*/
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unsigned int memory:1;
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/* Debug access that can even write to ROM. */
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unsigned int debug:1;
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/* Requester ID (for MSI for example) */
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unsigned int requester_id:16;
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/*
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* PID (PCI PASID) support: Limited to 8 bits process identifier.
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*/
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unsigned int pid:8;
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/*
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* Bus masters which don't specify any attributes will get this
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* (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
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* distinguish "all attributes deliberately clear" from
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* "didn't specify" if necessary. "debug" can be set alongside
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* "unspecified".
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*/
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bool unspecified;
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uint8_t _reserved1;
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uint16_t _reserved2;
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} MemTxAttrs;
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QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8);
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/* Bus masters which don't specify any attributes will get this,
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* which has all attribute bits clear except the topmost one
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* (so that we can distinguish "all attributes deliberately clear"
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* from "didn't specify" if necessary).
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*/
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#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = true })
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/* New-style MMIO accessors can indicate that the transaction failed.
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* A zero (MEMTX_OK) response means success; anything else is a failure
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* of some kind. The memory subsystem will bitwise-OR together results
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* if it is synthesizing an operation from multiple smaller accesses.
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*/
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#define MEMTX_OK 0
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#define MEMTX_ERROR (1U << 0) /* device returned an error */
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#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
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#define MEMTX_ACCESS_ERROR (1U << 2) /* access denied */
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typedef uint32_t MemTxResult;
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#endif
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