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qemu/tests/tcg/tricore
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Bastian Koppelmann fa581531ff tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT 
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08 09:58:08 +01:00
..
link.ld tests/tcg/tricore: Add build infrastructure 2021-05-18 09:36:21 +01:00
macros.h tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT 2023-02-08 09:58:08 +01:00
Makefile.softmmu-target tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT 2023-02-08 09:58:08 +01:00
test_abs.S tests/tcg/tricore: Add macros to create tests and first test 'abs' 2021-05-18 09:36:21 +01:00
test_bmerge.S tests/tcg/tricore: Add bmerge test 2021-05-18 09:36:21 +01:00
test_clz.S tests/tcg/tricore: Add clz test 2021-05-18 09:36:21 +01:00
test_dvstep.S tests/tcg/tricore: Add dvstep test 2021-05-18 09:36:21 +01:00
test_fadd.S tests/tcg/tricore: Add fadd test 2021-05-18 09:36:21 +01:00
test_fmul.S tests/tcg/tricore: Add fmul test 2021-05-18 09:36:21 +01:00
test_ftoi.S tests/tcg/tricore: Add ftoi test 2021-05-18 09:36:21 +01:00
test_imask.S tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK 2023-02-08 09:57:31 +01:00
test_insert.S tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT 2023-02-08 09:58:08 +01:00
test_madd.S tests/tcg/tricore: Add madd test 2021-05-18 09:36:21 +01:00
test_msub.S tests/tcg/tricore: Add msub test 2021-05-18 09:36:21 +01:00
test_muls.S tests/tcg/tricore: Add muls test 2021-05-18 09:36:21 +01:00