Jonathan Cameron 14bd0f3865 hw/mem/cxl-type3: Add properties to control link speed and width ... To establish performance characteristics of a CXL device when used via a particular CXL topology (root ports, switches, end points) it is necessary to set the appropriate link speed and width in the PCI Express capability structure. Provide x-speed and x-link properties for this. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916173518.1843023-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2024-11-04 16:03:24 -05:00
..
cxl_type3.c	hw/mem/cxl-type3: Add properties to control link speed and width	2024-11-04 16:03:24 -05:00
cxl_type3_stubs.c	hw/cxl/events: Improve QMP interfaces and documentation for add/release dynamic capacity.	2024-07-03 18:14:07 -04:00
Kconfig	hw/cxl/device: Add a memory device (8.2.8.5)	2022-05-13 06:13:36 -04:00
memory-device-stubs.c	memory-device: move stubs out of stubs/	2024-04-18 11:17:27 +02:00
memory-device.c	hw/mem/memory-device: Remove legacy_align from memory_device_pre_plug()	2024-06-19 12:40:49 +02:00
meson.build	memory-device: move stubs out of stubs/	2024-04-18 11:17:27 +02:00
npcm7xx_mc.c	hw/*: Use type casting for SysBusDevice in NPCM7XX	2021-01-12 21:19:02 +00:00
nvdimm.c	nvdimm: Reject writing label data to ROM instead of crashing QEMU	2023-09-19 10:23:21 +02:00
pc-dimm.c	hw/mem/memory-device: Remove legacy_align from memory_device_pre_plug()	2024-06-19 12:40:49 +02:00
sparse-mem.c	*: Add missing includes of qemu/error-report.h	2023-03-22 15:06:57 +00:00
trace-events	docs: fix references to docs/devel/tracing.rst	2021-06-02 06:51:09 +02:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00