Cédric Le Goater ee48fef06c aspeed/smc: Reintroduce "dram-base" property for AST2700 ... The Aspeed SMC device model use to have a 'sdram_base' property. It was removed by commit d177892d4a ("aspeed/smc: Remove unused "sdram-base" property") because previous changes simplified the DMA transaction model to use an offset in RAM and not the physical address. The AST2700 SoC has larger address space (64-bit) and a new register DMA DRAM Side Address High Part (0x7C) is introduced to deal with the high bits of the DMA address. To be able to compute the offset of the DMA transaction, as done on the other SoCs, we will need to know where the DRAM is mapped in the address space. Re-introduce a "dram-base" property to hold this value. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>		2024-06-16 21:08:54 +02:00
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aspeed_smc.h	aspeed/smc: Reintroduce "dram-base" property for AST2700	2024-06-16 21:08:54 +02:00
bcm2835_spi.h	hw/ssi: Implement BCM2835 SPI Controller	2024-02-02 13:51:59 +00:00
ibex_spi_host.h	Do not include hw/hw.h if it is not necessary	2023-02-27 09:15:38 +01:00
imx_spi.h	hw/ssi: imx_spi: Use a macro for number of chip selects supported	2021-02-02 17:00:54 +00:00
mss-spi.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
npcm7xx_fiu.h	hw/ssi: NPCM7xx Flash Interface Unit device model	2020-09-14 14:24:59 +01:00
npcm_pspi.h	hw/ssi: Add Nuvoton PSPI Module	2023-02-16 16:00:48 +00:00
pl022.h	arm: Update infocenter.arm.com URLs	2021-02-11 11:50:14 +00:00
sifive_spi.h	include: Include headers where needed	2023-01-08 01:54:22 -05:00
ssi.h	hw/ssi: Introduce a ssi_get_cs() helper	2023-09-01 11:40:04 +02:00
stm32f2xx_spi.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
xilinx_spips.h	hw/ssi/xilinx_spips: fix an out of bound access	2023-11-27 15:38:43 +00:00
xlnx-versal-ospi.h	hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models	2023-11-27 15:38:43 +00:00