Daniel Henrique Barboza 257cfaed47 docs/system/riscv: update 'virt' machine core limit ... The 'virt' RISC-V machine does not have a 8 core limit. The current limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at this moment. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231020200247.334403-2-dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-11-07 11:02:17 +10:00
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microchip-icicle-kit.rst	docs: Format literals correctly	2021-08-02 11:42:38 +01:00
shakti-c.rst	Fix some typos in documentation (found by codespell)	2021-11-22 15:02:38 +01:00
sifive_u.rst	docs/system/riscv: sifive_u: Update U-Boot instructions	2021-09-21 07:56:49 +10:00
virt.rst	docs/system/riscv: update 'virt' machine core limit	2023-11-07 11:02:17 +10:00