Daniel Henrique Barboza f31ba686a9 target/riscv/cpu.c: add 'sdtrig' in riscv,isa ... We have support for sdtrig for awhile but we are not advertising it. It is enabled by default via the 'debug' flag. Use the same flag to also advertise sdtrig. Add an exception in disable_priv_spec_isa_exts() to avoid spamming warnings for 'sdtrig' for vendor CPUs like sifive_u. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250604174329.1147549-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2025-07-04 21:09:48 +10:00
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acpi	target/riscv/cpu.c: add 'sdtrig' in riscv,isa	2025-07-04 21:09:48 +10:00
hex-loader	tests: Move tests/hex-loader-check-data/ to tests/data/hex-loader/	2018-11-05 13:23:46 -05:00
qobject	target/cris: Remove the deprecated CRIS target	2024-09-13 20:11:13 +02:00
smbios	tests: smbios: add test for legacy mode CLI options	2024-03-18 08:42:45 -04:00
uefi-boot-images	tests/data/uefi-boot-images: Add ISO image for LoongArch system	2025-06-01 06:38:53 -04:00
test-qga-config	qga: Replace 'blacklist' command line and config file options by 'block-rpcs'	2022-09-20 12:37:00 +02:00
test-qga-os-release	test-qga: add test for guest-get-osinfo	2017-07-18 05:49:01 -05:00