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Initial definitions for a simple machine using an AST2600 SoC (Cortex CPU). The Cortex CPU and its interrupt controller are too complex to handle in the common Aspeed SoC framework. We introduce a new Aspeed SoC class with instance_init and realize handlers to handle the differences with the AST2400 and the AST2500 SoCs. This will add extra work to keep in sync both models with future extensions but it makes the code clearer. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-19-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
121 lines
2.7 KiB
C
121 lines
2.7 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_SOC_H
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#define ASPEED_SOC_H
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#include "hw/cpu/a15mpcore.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/misc/aspeed_xdma.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/timer/aspeed_rtc.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#include "hw/net/ftgmac100.h"
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#include "target/arm/cpu.h"
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#include "hw/gpio/aspeed_gpio.h"
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#include "hw/sd/aspeed_sdhci.h"
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#define ASPEED_SPIS_NUM 2
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#define ASPEED_WDTS_NUM 4
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#define ASPEED_CPUS_NUM 2
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#define ASPEED_MACS_NUM 2
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typedef struct AspeedSoCState {
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/*< private >*/
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DeviceState parent;
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/*< public >*/
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ARMCPU cpu[ASPEED_CPUS_NUM];
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uint32_t num_cpus;
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A15MPPrivState a7mpcore;
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MemoryRegion sram;
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AspeedVICState vic;
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AspeedRtcState rtc;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedSCUState scu;
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AspeedXDMAState xdma;
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AspeedSMCState fmc;
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AspeedSMCState spi[ASPEED_SPIS_NUM];
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AspeedSDMCState sdmc;
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AspeedWDTState wdt[ASPEED_WDTS_NUM];
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FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
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AspeedGPIOState gpio;
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AspeedGPIOState gpio_1_8v;
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AspeedSDHCIState sdhci;
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} AspeedSoCState;
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#define TYPE_ASPEED_SOC "aspeed-soc"
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#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
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typedef struct AspeedSoCClass {
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DeviceClass parent_class;
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const char *name;
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const char *cpu_type;
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uint32_t silicon_rev;
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uint64_t sram_size;
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int spis_num;
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int wdts_num;
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const int *irqmap;
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const hwaddr *memmap;
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uint32_t num_cpus;
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} AspeedSoCClass;
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#define ASPEED_SOC_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
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#define ASPEED_SOC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
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enum {
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ASPEED_IOMEM,
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ASPEED_UART1,
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ASPEED_UART2,
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ASPEED_UART3,
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ASPEED_UART4,
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ASPEED_UART5,
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ASPEED_VUART,
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ASPEED_FMC,
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ASPEED_SPI1,
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ASPEED_SPI2,
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ASPEED_VIC,
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ASPEED_SDMC,
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ASPEED_SCU,
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ASPEED_ADC,
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ASPEED_SRAM,
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ASPEED_SDHCI,
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ASPEED_GPIO,
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ASPEED_GPIO_1_8V,
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ASPEED_RTC,
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ASPEED_TIMER1,
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ASPEED_TIMER2,
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ASPEED_TIMER3,
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ASPEED_TIMER4,
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ASPEED_TIMER5,
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ASPEED_TIMER6,
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ASPEED_TIMER7,
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ASPEED_TIMER8,
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ASPEED_WDT,
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ASPEED_PWM,
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ASPEED_LPC,
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ASPEED_IBT,
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ASPEED_I2C,
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ASPEED_ETH1,
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ASPEED_ETH2,
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ASPEED_SDRAM,
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ASPEED_XDMA,
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};
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#endif /* ASPEED_SOC_H */
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