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![]() - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAl9aa4YACgkQIeENKd+X cFTJjgf5ASfFIO5HqP1l80/UM5Pswyq0IROZDq0ItZa6U4EPzLXoE2N0POriIj4h Ds2JbMg0ORDqY0VbSxHlgYHMgJ9S6cuVOMnATsPG0d2jaJ3gSxLBu5k/1ENqe+Vw sSYXZv5uEAUfOFz99zbuhKHct5HzlmBFW9dVHdflUQS+cRgsSXq27mz1BvZ8xMWl lMhwubqdoNx0rOD3vKnlwrxaf54DcJ2IQT3BtTCjEar3tukdNaLijAuwt2hrFyr+ IwpeFXA/NWar+mXP3M+BvcLaI33j73/ac2+S5SJuzHGp/ot5nT5gAuq3PDEjHMeS t6z9Exp776VXxNE2iUA5NB65Yp3/6w== =07oA -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/riscv/trace-events |
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.. | ||
macio | ||
a9scu.h | ||
allwinner-cpucfg.h | ||
allwinner-h3-ccu.h | ||
allwinner-h3-dramc.h | ||
allwinner-h3-sysctrl.h | ||
allwinner-sid.h | ||
arm11scu.h | ||
arm_integrator_debug.h | ||
armsse-cpuid.h | ||
armsse-mhu.h | ||
aspeed_scu.h | ||
aspeed_sdmc.h | ||
aspeed_xdma.h | ||
auxbus.h | ||
avr_power.h | ||
bcm2835_mbox.h | ||
bcm2835_mbox_defs.h | ||
bcm2835_mphi.h | ||
bcm2835_property.h | ||
bcm2835_rng.h | ||
bcm2835_thermal.h | ||
cbus.h | ||
empty_slot.h | ||
grlib_ahb_apb_pnp.h | ||
imx6_ccm.h | ||
imx6_src.h | ||
imx6ul_ccm.h | ||
imx7_ccm.h | ||
imx7_gpr.h | ||
imx7_snvs.h | ||
imx25_ccm.h | ||
imx31_ccm.h | ||
imx_ccm.h | ||
imx_rngc.h | ||
iotkit-secctl.h | ||
iotkit-sysctl.h | ||
iotkit-sysinfo.h | ||
ivshmem.h | ||
mac_via.h | ||
max111x.h | ||
mips_cmgcr.h | ||
mips_cpc.h | ||
mips_itu.h | ||
mos6522.h | ||
mps2-fpgaio.h | ||
mps2-scc.h | ||
msf2-sysreg.h | ||
nrf51_rng.h | ||
pca9552.h | ||
pca9552_regs.h | ||
pvpanic.h | ||
sifive_e_prci.h | ||
sifive_test.h | ||
sifive_u_otp.h | ||
sifive_u_prci.h | ||
stm32f2xx_syscfg.h | ||
stm32f4xx_exti.h | ||
stm32f4xx_syscfg.h | ||
tmp105_regs.h | ||
tz-mpc.h | ||
tz-msc.h | ||
tz-ppc.h | ||
unimp.h | ||
vmcoreinfo.h | ||
zynq-xadc.h |