Anup Patel fe93582cf5 sifive_u: Add clock DT node for GEM ethernet ... The GEM ethernet on SiFive unleashed has fixed input clock of 125MHz as-per SiFive FU540 manual. This patch updates FDT generation for QEMU sifive_u machine to provide fixed-rate clock for GEM ethernet. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-12-20 12:03:12 -08:00
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riscv_hart.h	RISC-V HART Array	2018-03-07 08:30:28 +13:00
riscv_htif.h	RISC-V HTIF Console	2018-03-07 08:30:28 +13:00
sifive_clint.h	RISC-V: Replace hardcoded constants with enum values	2018-05-06 10:39:38 +12:00
sifive_e.h	hw/riscv/sifive_e: Create a SiFive E SoC object	2018-07-05 15:24:25 -07:00
sifive_plic.h	RISC-V: Use atomic_cmpxchg to update PLIC bitmaps	2018-09-04 13:19:31 -07:00
sifive_prci.h	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.h	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.h	sifive_u: Add clock DT node for GEM ethernet	2018-12-20 12:03:12 -08:00
sifive_uart.h	SiFive RISC-V UART Device	2018-03-07 08:30:28 +13:00
spike.h	RISC-V: Make some header guards more specific	2018-05-06 10:39:38 +12:00
virt.h	hw/riscv/virt: Connect the gpex PCIe	2018-12-20 11:45:20 -08:00